Wire bonding between isolation capacitors for multichip modules

Patent metadata

Field	Value
Publication number	US-10366958-B2
Application number	US-201715857234-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

First claim

The invention claimed is:

1. A packaged multichip device having reinforced isolation, comprising:
a first integrated circuit (IC) die on a first die pad including functional circuitry with a metal stack thereon including a top metal layer and a plurality of lower metal layers, at least a first isolation capacitor (first ISO cap) utilizing said top metal layer as a first top plate having a top dielectric layer thereon with a top plate dielectric aperture and one of said plurality of lower metal layers as its first bottom plate;
a second IC die on a second die pad including functional circuitry with a metal stack thereon including a top metal layer and a plurality of lower metal layers, including at least a second ISO cap utilizing said top metal layer as a second top plate having a top dielectric layer thereon having a top plate dielectric aperture and one of said plurality of lower metal layers as its second bottom plate;
a first end of a bondwire coupled within said top plate dielectric aperture on said first top plate, and
a second end of said bondwire coupled within said top plate dielectric aperture on said second top plate,
wherein said second end of said bondwire includes a stitch bond including a wire approach angle that is not normal to said second top plate, and
wherein said stitch bond is asymmetrically placed so that a center of said stitch bond is positioned at least 5% further from an outer edge of said second top plate on a bondwire crossover side as compared to a distance of said center of said stitch bond from a side opposite to said bondwire crossover side.

2. The packaged multichip device of claim 1 , wherein said IC die each include a plurality of said ISO caps.

3. The packaged multichip device of claim 1 , wherein said top dielectric layer extends over said second top plate at least 80% more on said bondwire crossover side as compared to a distance said top dielectric layer extends over said second top plate from said side opposite to said bondwire crossover side.

4. The packaged multichip device of claim 1 , wherein said first ISO cap and said second ISO cap both have silicon oxide as their capacitor dielectric layer.

5. The packaged multichip device of claim 4 , wherein a thickness of said capacitor dielectric layer is at least 4 μm, and wherein said first ISO cap and said second ISO cap both provide a breakdown voltage of at least 2,000 Volts.

6. The packaged multichip device of claim 1 , further comprising a mold compound which surrounds said bondwire.

7. The packaged multichip device of claim 1 , wherein said wire approach angle is at least 30° relative to said top plate of said second die.

8. The packaged multichip device of claim 1 , wherein said center of said stitch bond is positioned at least 50% further from said outer edge of said second top plate.

9. The packaged multichip device of claim 1 , wherein said first IC die comprises a transmitter and wherein said second IC die comprises a receiver.

10. The packaged multichip device of claim 1 , wherein said top dielectric layer comprises a first dielectric layer on a second dielectric layer.

11. A method of assembling a packaged multichip device having reinforced isolation, comprising:
placing a first integrated circuit (IC) die on a first die pad including functional circuitry with a metal stack thereon including a top metal layer and a plurality of lower metal layers, including at least a first isolation capacitor (first ISO cap) utilizing said top metal layer a first top plate having a top dielectric layer thereon with a top plate aperture and one of said plurality of lower metal layers as its bottom plate;
placing a second IC die on a second die pad including functional circuitry with a metal stack thereon including a top metal layer and a plurality of lower metal layers, including at least a second ISO cap utilizing said top metal layer a second top plate having a top dielectric layer thereon having a top plate aperture and one of said plurality of lower metal layers as its bottom plate;
bonding a first end of a bondwire within said top plate aperture on said first top plate;
bonding a second end of said bondwire within said top plate aperture on said second top plate, wherein said second end of said bondwire includes a stitch bond including a wire approach angle that is not normal to said top plate of said second die;
wherein said stitch bond is an asymmetrically placed bond so that a center of said stitch bond is at least 5% further from an outer edge of said second top plate on a bondwire crossover side as compared to a distance of said center of said stitch bond from a side opposite to said bondwire crossover side.

12. The method of claim 11 , wherein said IC die each include a plurality of said ISO caps.

13. The method of claim 11 , wherein said top dielectric layer extends over said second top plate at least 80% more on said bondwire crossover side as compared to a distance said top dielectric layer extends over said second top plate from said side opposite to said bondwire crossover side.

14. The method of claim 11 , wherein said first ISO cap and said second ISO cap both have silicon oxide as their capacitor dielectric layer.

15. The method of claim 14 , wherein a thickness of said capacitor dielectric layer is at least 4 μm, and wherein said first ISO cap and said second ISO cap both provide a breakdown voltage of at least 2,000 Volts.

16. The method of claim 11 , further comprising forming a mold compound which surrounds said bondwire.

17. The method of claim 11 , wherein said wire approach angle is at least 25° relative to said top plate of said second die.

18. The method of claim 11 , wherein said center of said stitch bond is positioned at least 50% further from said outer edge of said second top plate.

19. The method of claim 11 , wherein said first IC die comprises a transmitter and wherein said second IC die comprises a receiver.

20. The method of claim 11 , wherein said top dielectric layer comprises a first dielectric layer on a second dielectric layer.

Assignees

• Texas Instruments Inc

Inventors

• Bonifield Thomas Dyer
• West Jeffrey Alan
• Williams Byron Lovell

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title