Multi-die stacked power delivery

Patent metadata

Field	Value
Publication number	US-11960339-B2
Application number	US-202117371459-A
Country	US
Kind code	B2
Filing date	Jul 9, 2021
Priority date	Jul 9, 2021
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A multi-die processor semiconductor package includes a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a unique power domain to each of the first plurality of compute dies. In some embodiments, the semiconductor package also includes a second base IC die including a second plurality of compute dies 3D stacked on top of the second base IC die and an interconnect communicably coupling the first base IC die to the second base IC die.

First claim

What is claimed is:

1. A processor, comprising:
a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies stacked on top of the first base IC die, a different power domain to each of the first plurality of compute dies, each of the different power domains corresponding to a different power plane,
wherein the first base IC die is configured to unify power domains of two or more voltage regulator networks of a plurality of voltage regulator networks to provide a first independent power plane to a first compute die of the first plurality of compute dies.

2. The processor of claim 1 , further comprising:
one or more present bits positioned at an interface between the first base IC die and the first plurality of compute dies, wherein the one or more present bits indicate a first value for a first hardware configuration including the first plurality of compute dies stacked on top of the first base IC die.

3. The processor of claim 1 , wherein the first base IC die includes the plurality of voltage regulator networks for providing power to the different power domain of each of the first plurality of compute dies.

4. The processor of claim 3 , wherein a first voltage regulator provides a second independent power domain to a second compute die of the first plurality of compute dies.

5. The processor of claim 3 , further comprising:
a plurality of voltage regulator controllers, wherein each of the plurality of voltage regulator controllers is configured to control, based at least in part on the indication of the configuration of the first plurality of compute dies, one or more of the plurality of voltage regulator networks.

6. The processor of claim 3 , further comprising:
an input power rail providing a single power supply to the plurality of voltage regulator networks of the first base IC die.

7. A system, comprising:
a processor multi-chip module communicably coupled to a host processor, wherein the processor multi-chip module includes:
a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a different power domain to each of the first plurality of compute dies, each of the different power domains corresponding to a different power plane,
wherein the first base IC dies is configured to unify power domains of two or more voltage regulator networks of a plurality of voltage regulator networks to provide a first independent power plane to a first compute die of the first plurality of compute dies.

8. The system of claim 7 , wherein the indication of the configuration signals a type of compute die of the first plurality of compute dies 3D stacked on top of the first base IC die, wherein a first compute die of the first plurality of compute dies includes a different hardware configuration relative to the configuration of a second compute die of the first plurality of compute dies, wherein, based on the type of compute die of the first plurality of compute dies 3D stacked on top of the first base IC die, the first base IC die provides a first power domain providing a first independent power plane to the first compute die and a second power domain providing a second independent power plane to the second compute die.

9. The system of claim 7 , further comprising:
one or more present bits positioned at an interface between the first base IC die and the first plurality of compute dies, wherein the one or more present bits indicate a first value for a first hardware configuration including the first plurality of compute dies 3D stacked on top of the first base IC die.

10. The system of claim 7 , wherein the first base IC die includes the plurality of voltage regulator networks for providing power to the different power domain of each of the first plurality of compute dies.

11. The system of claim 10 , wherein a first voltage regulator provides a second independent power domain to a second compute die of the first plurality of compute dies.

12. The system of claim 10 , further comprising:
a plurality of voltage regulator controllers, wherein each of the plurality of voltage regulator controllers is configured to control, based at least in part on the indication of the configuration of the first plurality of compute dies, one or more of the plurality of voltage regulator networks.

13. An integrated circuit device, comprising:
a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a unique power domain to each of the first plurality of compute dies, each unique power domain corresponding to a different power plane,
wherein the first base IC die is configured to unify power domains of two or more voltage regulator networks of a plurality of voltage regulator networks to provide a first independent power plane to a first compute die of the first plurality of compute dies.

14. The integrated circuit device of claim 13 , wherein the first base IC die includes the plurality of voltage regulator networks for providing power to the unique power domain of each of the first plurality of compute dies.

15. The integrated circuit device of claim 14 , wherein a first voltage regulator provides a second independent power domain to a second compute die of the first plurality of compute dies.

16. The integrated circuit device of claim 15 , further comprising:
a plurality of voltage regulator controllers, wherein each of the plurality of voltage regulator controllers is configured to control, based at least in part on the indication of the configuration of the first plurality of compute dies, one or more of the voltage regulator networks.

17. The integrated circuit device of claim 15 , further comprising:
an input power rail providing a single power supply to the plurality of voltage regulator networks of the first base IC die.

Assignees

• Advanced Micro Devices Inc

Inventors

• Chapman Eric J
• Smith Alan D
• Chang Edward

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• H10W72/60

  Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title

• H01L25/18

  Electricity · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title