Display panel and display device for IVL testing

Patent metadata

Field	Value
Publication number	US-11957013-B2
Application number	US-202017260248-A
Country	US
Kind code	B2
Filing date	Mar 27, 2020
Priority date	Mar 27, 2020
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

A display panel includes: a silicon-based substrate, a driving layer, a first electrode layer, an organic light emitting layer, a second electrode layer and a plurality of pads. The display signal access pad is configured to access the display signal during a display phase, the test signal access pad at least includes a first group of test phase access pads, and the first group of test phase access pads includes a first pad and a second pad, the first pad is electrically connected with the electrode ring, and the second pad is electrically connected with the silicon-based substrate.

First claim

What is claimed is:

1. A display panel, comprising:
a silicon-based substrate, comprising a display region and a peripheral region surrounding the display region;
a driving layer, formed in the silicon-based substrate, and comprising a plurality of first transistors located in the display region;
a first electrode layer, disposed on a side of the driving layer away from the silicon-based substrate, and comprising a plurality of first electrodes located in the display region, and each of the first electrodes is electrically connected to each of the first transistors;
an organic light emitting layer, disposed on a side of the first electrode layer away from the driving layer;
a second electrode layer, disposed on a side of the organic light emitting layer away from the driving layer, and comprising a second electrode located in the display region and an electrode ring located in the peripheral region, the electrode ring being configured to surround the second electrode and being connected to the second electrode; and
a plurality of pads, located in the peripheral region at least one side of the display region, the plurality of pads comprising a display signal access pad and a test signal access pad, and the test signal access pad being located at both sides of the display signal access pad;
wherein the display signal access pad is configured to access the display signal during a display phase, and the test signal access pad is configured to access the test signal during a test phase, the test signal access pad at least comprises a first group of test phase access pads, and the first group of test phase access pads comprises a first pad and a second pad, the first pad is electrically connected with the electrode ring, and the second pad is electrically connected with the silicon-based substrate.

2. The display panel according to claim 1 , wherein each of the first transistors comprises an active region formed in the silicon-based substrate, two doped regions located in the active region, a channel region located between the two doped regions, and a gate electrode located on the channel region, the two doped regions respectively form a first pole and a second pole, and the second pad is electrically connected to the active region of each of the first transistors.

3. The display panel according to claim 2 , wherein the driving layer comprises:
a gate insulating layer, being disposed on the channel region on a side of the silicon-based substrate;
a gate layer, being disposed on a side of the gate insulating layer away from the silicon-based substrate;
a first planarization layer, being disposed on a side of the silicon-based substrate and being configured to cover the gate insulating layer and the gate layer;
a first conductive layer, being disposed on a side of the first planarization layer away from the silicon-based substrate;
a dielectric layer, being provided on a side of the first planarization layer away from the silicon-based substrate and being configured to cover the first conductive layer;
a second conductive layer, being disposed on a side of the dielectric layer away from the silicon-based substrate; and
a second planarization layer, being disposed on a side of the dielectric layer away from the silicon-based substrate and being configured to cover the second conductive layer, and the first electrode layer being located on a side of the second planarization layer away from the silicon-based substrate.

4. The display panel according to claim 2 , wherein the test signal access pad also comprises a second group of test phase access pads, and the second group of test phase access pads comprise a third pad and a fourth pad, the third pad is electrically connected to the electrode ring, and the fourth pad is electrically connected to the silicon-based substrate.

5. The display panel according to claim 1 , wherein the test signal access pad further comprises a second group of test phase access pads, and the second group of test phase access pads comprise a third pad and a fourth pad, the third pad is electrically connected to the electrode ring, and the fourth pad is electrically connected to the silicon-based substrate.

6. The display panel according to claim 5 , wherein the peripheral region comprises a bonding area, the third pad, the fourth pad and a plurality of display signal access pads are located in the bonding area.

7. The display panel according to claim 6 , wherein the first pad and the third pad are located on a same side of the display signal access pad, and the second pad and the fourth pad are located on other side of the display signal access pad.

8. The display panel according to claim 6 , wherein the third pad and the fourth pad are respectively arranged adjacent to the display signal access pad.

9. The display panel according to claim 5 , wherein the first pad and the third pad are located on a same side of the display signal access pad, and the second pad and the fourth pad are located on other side of the display signal access pad.

10. The display panel according to claim 9 , wherein the third pad and the fourth pad are respectively arranged adjacent to the display signal access pad.

11. The display panel according to claim 5 , wherein the third pad and the fourth pad are respectively arranged adjacent to the display signal access pad.

12. The display panel according to claim 5 , wherein the display panel is provided with one first pad and one second pad.

13. The display panel according to claim 12 , wherein the display panel is provided with one third pad and one fourth pad.

14. The display panel according to claim 13 , wherein the third pad is connected to the first pad, the fourth pad is connected to the second pad.

15. The display panel according to claim 5 , wherein the display panel further comprises:
a connection line being electrically connected to the second pad and the fourth pad; and
a plurality of detection lines being connected to the connection line, wherein each of the detection lines is electrically connected to the active region of a row of first transistors respectively.

16. The display panel according to claim 5 , wherein the first pad is electrically connected to the electrode ring through a conducting wire.

17. The display panel according to claim 5 , wherein the display panel further comprises:
a second transistor formed in the peripheral region of the silicon-based substrate, and comprising an active region formed in the silicon-based substrate, two doped regions in the active region, a channel region between the two doped regions, and a gate electrode located on the channel region, the two doped regions forming a first pole and a second pole respectively; and
the second pole of the second transistor is electrically connected to the electrode ring, and the first pad is electrically connected to the first pad and the gate electrode of the second transistor.

18. The display panel according to claim 5 , wherein the display panel further comprises:
a first packaging layer disposed on a side of the second electrode layer away from the organic light emitting layer;
a color film layer disposed on a side of the first packaging layer away from the second electrode layer; and
a second packaging layer disposed on a side of the color film layer away from the first packaging layer, the third pad and the fourth pad being exposed from the second packaging layer.

19. The display panel according to claim 1 , wherein the test signal access pad and the first electrode are arranged in the same

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhu Zhijian
• Lu Pengcheng
• Ao Yu
• Li Yunlong
• Tian Yuanlan

Classifications

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10P74/00

  Testing or measuring during manufacture or treatment of wafers, substrates or devices · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09G3/006

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• H10K50/844

  Encapsulations · CPC title