Display device, test circuit, and test method thereof

Patent metadata

Field	Value
Publication number	US-2019197930-A1
Application number	US-201816224324-A
Country	US
Kind code	A1
Filing date	Dec 18, 2018
Priority date	Dec 21, 2017
Publication date	Jun 27, 2019
Grant date	—

Abstract

The embodiments of the present disclosure relate to a display device, a test circuit, and a test method thereof. More specifically, a display device may include a silicon substrate having a plurality of gate lines, a plurality of data lines, a plurality of sensing lines, and a pixel array on which a plurality of subpixels are arranged; a test circuit arranged on the silicon substrate, the test circuit configured to select at least one line of the plurality of data lines or the plurality of sensing lines, to convert a signal transmitted through the selected line into a digital signal, and to output test data; and a test pad unit configured to output the test data to a circuit outside the silicon substrate.

First claim

What is claimed is:

1 . A display device, comprising:
a silicon substrate having a plurality of gate lines, a plurality of data lines, a plurality of sensing lines, and a pixel array on which a plurality of subpixels are arranged; a test circuit arranged on the silicon substrate, the test circuit configured to select at least one line of the plurality of data lines or the plurality of sensing lines, to convert a signal transmitted through the selected line into a digital signal, and to output test data; and a test pad unit configured to output the test data to a circuit outside the silicon substrate.

2 . The display device of claim 1 , wherein the test circuit comprises:
a first test multiplexer configured to select one of the plurality of data lines or the plurality of sensing lines according to a test mode; a second test multiplexer configured to select at least one line of the plurality of data lines or plurality of sensing lines selected by the first test multiplexer; and a test converter configured to convert a signal received through the line selected by the second test multiplexer into a digital signal and to output the test data having a predetermined number of bits.

3 . The display device of claim 2 , wherein the second test multiplexer sequentially changes and selects at least one line of the plurality of data lines or plurality of sensing lines selected by the first test multiplexer.

4 . The display device of claim 2 , wherein the test converter further comprises:
an analog-to-digital converter; and a signal converter configured to be arranged between the second test multiplexer and the analog-to-digital converter and to convert, when a signal output from the second test multiplexer is a current signal, the current signal into a voltage signal to output the converted result to the analog-to-digital converter.

5 . The display device of claim 4 , wherein the signal converter comprises:
a current-voltage converter configured to detect a current of the signal output from the second test multiplexer and to convert the detected current into a corresponding voltage signal; and a third test multiplexer configured to output, when a mode designated by a test mode signal is a sensing test mode, an output of the current-voltage converter to the analog-to-digital converter, and to output, when the mode designated by the test mode signal is a data test mode, an output of the second test multiplexer to the analog-to-digital converter.

6 . The display device of claim 4 , wherein the test pad unit comprises:
the same number of test pads as the number of bits of the test data; and a reference pad configured to be applied with a data reference voltage of the analog-to-digital converter from an external device.

7 . The display device of claim 2 , further comprising:
a driving circuit configured to be arranged on a circuit zone; wherein the driving circuit comprises:
at least one gate driving circuit configured to be arranged in a first direction in which the plurality of gate lines of the pixel array extend and to drive the plurality of gate lines;
at least one source driving circuit configured to be arranged in a second direction in which the plurality of data lines of the pixel array extend and to drive the plurality of data lines; and
a controller configured to control the at least one gate driving circuit, the at least one source driving circuit, and the test circuit.

8 . The display device of claim 7 , wherein the test circuit is arranged in a margin area in which the at least one gate driving circuit and the at least one source driving circuit are not located in a periphery of the pixel array.

9 . The microdisplay device of claim 7 , further comprising:
an input/output pad unit configured to receive input image data from an external device and to transmit the received input image data to the controller, wherein the test pad unit is arranged adjacent to the input/output pad unit.

10 . The microdisplay device of claim 7 , wherein the first test multiplexer is arranged inside the at least one source driving circuit.

11 . The display device of claim 2 , wherein the second test multiplexer and the test converter are arranged adjacent to the first test multiplexer.

12 . The display device of claim 6 , wherein the data reference voltage is a stepwisely increasing voltage generated by a single slope generator.

13 . The display device of claim 12 , wherein the single slope generator is arranged in a margin area in which at least one gate driving circuit and at least one source driving circuit in a driving circuit included in the display device are not located.

14 . A test circuit of a microdisplay device which is arranged on a silicon substrate, wherein the test circuit selects at least one line of a plurality of data lines or a plurality of sensing lines arranged on a pixel array, converts a signal transmitted through the selected line into a digital signal to acquire test data, and outputs the acquired test data through a test pad unit arranged on the silicon substrate.

15 . The test circuit of claim 14 , further comprising:
a first test multiplexer configured to select one of the plurality of data lines or the plurality of sensing lines according to a test mode; a second test multiplexer configured to select at least one line of the plurality of data lines or the plurality of sensing lines selected by the first test multiplexer; and a test converter configured to convert a signal received through the line selected by the second test multiplexer into a digital signal, and to output the test data having a predetermined number of bits, wherein the second test multiplexer and the test converter are arranged adjacent to the first test multiplexer.

16 . The test circuit of claim 14 , wherein the test pad unit comprises:
the same number of test pads as the number of bits of the test data, and a reference pad configured to be applied with a data reference voltage from a single slope generator, wherein the single slope generator is arranged in a margin area.

17 . A method of testing a microdisplay device including a silicon substrate configured to include a plurality of gate lines, a plurality of data lines, a plurality of sensing lines, and a pixel array on which a plurality of subpixels are arranged; a test circuit; and a test pad unit, the method comprising:
selecting one of the plurality of data lines or the plurality of sensing lines according to a test mode; selecting at least one line of the selected plurality of data lines or sensing lines; and converting a signal received through the selected line to output the test data having a predetermined number of bits using an analog-to-digital converter.

Assignees

• Lg Display Co Ltd

Inventors

• Kim Beom-Jin
• Shin Sunkyung
• Kwak Bongchoon
• Jung Sojung

Classifications

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title