Display panel and repairing method thereof

Patent metadata

Field	Value
Publication number	US-2016204181-A1
Application number	US-201514731814-A
Country	US
Kind code	A1
Filing date	Jun 5, 2015
Priority date	Jan 13, 2015
Publication date	Jul 14, 2016
Grant date	—

Abstract

A display panel and a repairing method thereof are disclosed. In one aspect, the display panel includes an active area including a plurality of pixels and a plurality of signal lines. The panel also includes a repair line at least partially surrounding the active area and overlapping the signal line in the active area and a plurality of first transistors formed on a side of the active area, wherein one end of each of the first transistors overlaps the repair line. The panel further includes a sealing portion configured to seal the active area, the repair line, and the first transistors. The panel also includes a pad portion formed outside the sealing portion and including a plurality of dummy pads respectively connected to the first transistors and a plurality of driving pads respectively connected to the signal lines.

First claim

What is claimed is:

1 . A display panel, comprising:
an active area including a plurality of pixels and a plurality of signal lines; a repair line at least partially surrounding the active area and overlapping the signal line in the active area; a plurality of first transistors formed on a side of the active area, wherein one end of each of the first transistors overlaps the repair line; a sealing portion configured to seal the active area, the repair line, and the first transistors; a pad portion formed outside the sealing portion and including i) a plurality of dummy pads respectively connected to the first transistors and ii) a plurality of driving pads respectively connected to the signal lines; and a plurality of test signal lines connected to the corresponding dummy and driving pads and configured to provide test signals from the dummy pads and the driving pads to the pixels.

2 . The display panel of claim 1 , wherein a defective one of the signal lines is electrically connected to the overlapping repair line.

3 . The display panel of claim 2 , wherein each of the first transistors is selectively connected to the repair line based on a type of test signal provided to the defective signal line.

4 . The display panel of claim 2 , wherein the defective signal line includes a defect point and a peripheral point adjacent to the defect point, and wherein the peripheral point is configured to be cut.

5 . The display panel of claim 1 , further comprising a plurality of second transistors each including a first end electrically connected to the corresponding dummy pad, a second end electrically connected to a corresponding test signal line, and a gate electrically connected to the first transistors and a test starting signal line configured to receive a test starting signal from outside,the sealing portion.

6 . The display panel of claim 1 , wherein a first one of the first transistors has an end electrically connected to the repair line, and wherein a second one of the first transistors has an end isolated from the repair line based on a type of test signal provided to a defective one of the signal lines.

7 . The display panel of claim 1 , further comprising:
a repair pad formed outside the sealing portion and connected to the repair line; and a second transistor including a first end electrically connected to the repair pad, a second end overlapping the test signal lines, and a gate electrically connected to a test starting signal line configured to receive a test starting signal from outside the sealing portion.

8 . The display panel of claim 7 , wherein one of the test signal lines and the second end of the corresponding second transistor are electrically connected to each other based on a type of test signal supplied to a defective one of the signal lines.

9 . A method of repairing a display panel, comprising:
determining a defective one of a plurality of signal lines, wherein the display panel includes an active area including a plurality of pixels and the signal lines, a repair line at least partially surrounding the active area and overlapping the signal line and the active area, a plurality of first transistors formed on a side of the active area, wherein one end of each of the first transistors overlaps with the repair line; cutting a peripheral point adjacent to a defect point indicative of a defect in the defective signal line; selecting a first transistor of the first transistors based on a type of test signal provided to the defective signal line; and connecting the repair line to the selected first transistor based on the selection.

10 . The repairing method of claim 9 , further comprising supplying a test starting signal at a disable level when the selected first transistor and the repair line are electrically connected to each other,
wherein the display panel further includes:
a sealing portion configured to seal the active area, the repair line, and the first transistors;
a pad portion formed outside the sealing portion and including i) a plurality of dummy pads respectively connected to the first transistors and ii) a plurality of driving pads respectively connected to the signal lines; and
a plurality of second transistors having a first end electrically connected to a corresponding dummy pad among the dummy pads, a second end electrically connected to a corresponding test signal line, and a gate electrically connected to the selected first transistor and a test starting signal line to which a test starting signal is supplied from outside the sealing portion.

11 . The method of claim 9 , wherein a first one of the first transistors has an end electrically connected to the repair line, and wherein a second one of the first transistors has an end isolated from the repair line based on a kind of test signal provided to the defective signal line.

12 . The method of claim 9 , wherein the display panel further comprises:
a sealing portion configured to seal the active area, the repair line, and the first transistors; a pad portion formed outside the sealing portion and including i) a plurality of dummy pads respectively connected to the first transistors and ii) a plurality of driving pads respectively connected to the signal lines; a plurality of test signal lines connected to the corresponding dummy and driving pads and configured to provide test signals from the dummy pads and the driving pads to the pixels; a repair pad formed outside the sealing portion and connected to the repair line; and a second transistor having a first end electrically connected to the repair pad, a second end overlapping the test signal lines, and a gate electrically connected to a test starting signal line configured to receive a test starting signal from outside the sealing portion.

13 . The method of claim 12 , wherein one of the test signal lines and the second end of the corresponding second transistor are electrically connected to each other based on a kind of test signal supplied to the signal line with the defect.

14 . A display panel, comprising:
an active area including a plurality of pixels and a plurality of signal lines electrically connected to the pixels; a repair line formed at least partially surrounding the active area and overlapping the signal line in the active area; a plurality of first transistors formed on a side of the active area, wherein one end of each of the first transistors overlaps the repair line at an overlapping point; a sealing portion configured to seal the active area, the repair line, and the first transistors, wherein the sealing portion surrounds the active area; and a pad portion formed outside the sealing portion and including i) a plurality of dummy pads respectively connected to the first transistors and ii) a plurality of driving pads respectively connected to the signal lines; a gate signal line electrically connected to the gates of the first transistors and configured to transmit a test starting signal to the first transistors; and a direct current (DC) line electrically connected to the signal lines and configured to transmit a test signal and a data signal to the pixels.

15 . The display panel of claim 14 , wherein a defective one of the signal lines is electrically connected to the overlapping repair line.

16 . The display panel of claim 15 , wherein the DC line comprises R, G, B lines respectively connected to the corresponding dummy and driving pads, wherein the R, G, B lines are configured to provide the test signal from the dummy and driving pads to the pixels, wherein each of the first tra

Assignees

• Samsung Display Co Ltd

Inventors

• So Dong-Yoon
• Park Kyong Tae
• Yoon Mi Jin
• Cho Sung Ho
• Cho Yu-Hyun

Classifications

• H10K59/87

  Passivation; Containers; Encapsulations · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• G02F1/1345 Primary

  Conductors connecting electrodes to cell terminals · CPC title

• H01L27/3211

  Electricity · mapped topic

• H01L51/5237

  Electricity · mapped topic