Memory device and electronic system including the same

Patent metadata

Field	Value
Publication number	US-11956965-B2
Application number	US-202117212029-A
Country	US
Kind code	B2
Filing date	Mar 25, 2021
Priority date	Sep 16, 2020
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

A memory device and an electronic system, the memory device including a substrate; a ground selection line on the substrate, a cutting portion cutting the ground selection line; a first insulation layer and a first word line stacked immediately above the ground selection line; and second insulation layers and second word lines alternately stacked on the first word line, wherein the first word line includes a first portion laterally offset from the cutting portion and a second portion overlying the cutting portion, the first portion of the first word line has a first thickness, and the second portion of the first word line has a second thickness less than the first thickness.

First claim

What is claimed is:

1. A memory device, comprising:
a substrate;
a first insulation layer on the substrate:
a ground selection line on the first insulation layer, a cutting portion cutting the ground selection line;
an uppermost first insulation layer and a first word line stacked immediately above the ground selection line; and
second insulation layers and second word lines alternately stacked on the first word line,
wherein:
the first word line includes a first portion laterally offset from the cutting portion and a second portion overlying the cutting portion,
the first portion of the first word line has a first thickness,
the second portion of the first word line has a second thickness less than the first thickness,
each of the second word lines has the first thickness,
the cutting portion includes an opening passing through the uppermost first insulation layer, cutting the ground selection line, and extending into a portion of the first insulation layer,
a lower insulation pattern is in the opening, and
the uppermost first insulation layer has a thickness that is about 2 times to about 5 times a thickness of the first insulation layer.

2. The memory device as claimed in claim 1 , wherein an upper surface of the lower insulation pattern protrudes above a lower surface of the first word line at the first portion of the first word line.

3. The memory device as claimed in claim 1 , wherein the lower insulation pattern includes silicon oxide.

4. The memory device as claimed in claim 1 , wherein: an upper surface of the first word line is flat at the first portion and the second portion, and
a lower surface of the second portion of the first word line is inwardly recessed relative to a lower surface of the first portion of the first word line such that a lower surface of the first word line is not flat.

5. The memory device as claimed in claim 1 , wherein upper surfaces of the second word lines are flat and lower surfaces of the second word lines are flat.

6. The memory device as claimed in claim 1 , wherein the thickness of the uppermost first insulation layer is greater than a thickness of the second insulation layer.

7. The memory device as claimed in claim 1 , further comprising:
a circuit pattern on the substrate; and
a base semiconductor pattern on the circuit pattern,
wherein the ground selection line is on the base semiconductor pattern.

8. A memory device, comprising:
a substrate;
a circuit pattern on the substrate;
a base semiconductor pattern on the circuit pattern;
a first insulation layer on the base semiconductor pattern;
a ground selection line on the first insulation layer, a cutting portion cutting the ground selection line;
an uppermost first insulation layer and a first word line stacked immediately above the ground selection line;
a lower insulation pattern passing through a portion of the uppermost first insulation layer, the first insulation layer, and the cutting portion;
second insulation layers and second word lines alternately stacked on the first word line; and
a channel structure passing through the ground selection line, the uppermost first insulation layer, the first word line, the second insulation layers, and the second word lines, the channel structure extending in a vertical direction,
wherein:
the first word line includes a first portion laterally offset from the cutting portion and a second portion overlying the cutting portion,
the first portion of the first word line has a first thickness,
the second portion of the first word line has a second thickness less than the first thickness,
an upper surface of the lower insulation pattern protrudes above a lower surface of the first word line at the first portion of the first word line,
each of the second word lines has the first thickness, and
the uppermost first insulation layer has a thickness that is about 2 times to about 5 times a thickness of the first insulation layer.

9. The memory device as claimed in claim 8 , wherein:
an upper surface of the first word line is flat at the first portion and the second portion, and
a lower surface of the second portion of the first word line is inwardly recessed relative to a lower surface of the first portion of the first word line such that a lower surface of the first word line is not flat.

10. The memory device as claimed in claim 8 , wherein upper and lower surfaces of the second word lines are flat.

11. The memory device as claimed in claim 8 , further comprising a gate pattern of an erase control transistor below the ground selection line on the base semiconductor pattern.

12. The memory device as claimed in claim 8 , wherein the lower insulation pattern includes silicon oxide.

13. The memory device as claimed in claim 8 , wherein: the ground selection line, the uppermost first insulation layer, the first word line, the second insulation layers, and the second word lines stacked in the vertical direction constitute a cell stacked structure, and
each of a plurality of the cell stacked structures extend in a first direction.

14. The memory device as claimed in claim 13 , further comprising trenches extending in the first direction between the cell stacked structures and a connection portion between the trenches, wherein the cutting portion is under the connection portion.

15. An electronic system, comprising:
a memory device; and
a controller configured to control the memory device, the controller being electrically connected to the memory device through an input/output pad of the memory device,
wherein the memory device includes:
a substrate;
a peripheral circuit pattern on the substrate;
a first insulation layer on the peripheral circuit pattern;
a ground selection line on the first insulation layer, a cutting portion cutting the ground selection line;
an uppermost first insulation layer and a first word line stacked immediately above the ground selection line;
second insulation layers and second word lines alternately stacked on the first word line; and
the input/output pad, the input/output pad being electrically connected to the peripheral circuit pattern,

wherein the first word line includes a first portion laterally offset from the cutting portion and a second portion overlying the cutting portion,
wherein the first portion of the first word line has a first thickness,
wherein the second portion of the first word line has a second thickness less than the first thickness,
wherein each of the second word lines has the first thickness,
wherein the cutting portion includes an opening passing through the uppermost first insulation layer, cutting the ground selection line, and extending into a portion of the first insulation layer,
wherein a lower insulation pattern fills the opening, the lower insulation pattern having an upper surface protruding above a lower surface of the first word line at the first portion of the first word line and having a lower surface protruding below a lower surface of the ground selection line, and
the uppermost first insulation layer has a thickness that is about 2 times to about 5 times a thickness of the first insulation layer.

16. The memory device as claimed in claim 1 , wherein the substrate includes a first region in which memory cells are formed and a second region surrounding the first region in which contacts for transmitting electrical signals to memory cells are formed, and the cutting portion is disposed in the second region of the substrate.

17. The memory device as claimed in claim 8 , wherein the substrate includes a first

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Giyong
• Kim Jaehyung

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/41

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title