Adaptive pre-programming

Patent metadata

Field	Value
Publication number	US-11955182-B2
Application number	US-202217746616-A
Country	US
Kind code	B2
Filing date	May 17, 2022
Priority date	May 17, 2022
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

Adaptive and dynamic control of the duration of a pre-program pulse based on a number of planes selected for the pre-program operation is disclosed. A value for a pre-program time increment parameter may be selected based on the number of planes for which the pre-program operation will be performed or determined based on a predefined association with the number of planes. A pre-program voltage pulse may then be applied for a duration that is equal to a default duration for a single-plane pre-program operation incremented by the time increment parameter value. This approach solves the technical problem of Vt downshift for multi-plane pre-program operations, and thus, ensures that the success rate of secure erase operations does not diminish as the number of planes increases. This, in turn, allows for pre-program operations to be consistently performed on a multi-plane basis, which produces the technical effect of improved system performance.

First claim

What is claimed is:

1. A method of performing a pre-program operation on one or more memory blocks, the method comprising:
determining that the pre-program operation is to be performed;
determining a number of planes for which the pre-program operation is to be performed;
selecting a value for a pre-program time increment parameter based at least in part on the number of planes for which the pre-program operation is to be performed; and
performing the pre-program operation on the one or more memory blocks for the selected number of planes, wherein performing the pre-program operation comprises applying a pre-program voltage pulse for a duration corresponding to a sum of a baseline pre-program pulse duration and the selected value for the pre-program time increment parameter.

2. The method of claim 1 , wherein the number of planes is greater than one, and wherein the value of the pre-program time increment parameter is greater than zero.

3. The method of claim 1 , wherein the pre-program time increment parameter value increases non-linearly with an increase in the number of planes.

4. The method of claim 1 , wherein selecting the value for the pre-program time increment parameter comprises:
determining the pre-program time increment parameter value based on a predefined association with the selected number of planes; and
overriding an internal timer value with a new timer value, the new timer value being a sum of a default value representing the baseline pre-program pulse duration and the pre-program time increment parameter value.

5. The method of claim 1 , wherein selecting the value for the pre-program time increment parameter comprises identifying a user-selected value for the pre-program time increment parameter.

6. The method of claim 5 , wherein the user-selected value for the pre-program time increment parameter is selected from a continuous range of values.

7. The method of claim 5 , wherein the user-selected value for the pre-program time increment parameter is selected from a discrete set of values.

8. The method of claim 7 , wherein the pre-program time increment parameter is a multi-bit parameter, and wherein each value in the discrete set of values corresponds to a respective value of the multi-bit parameter.

9. The method of claim 1 , wherein selecting the value for the pre-program time increment parameter comprises selecting the value for the pre-program time increment parameter based on a trained machine learning model that receives the selected number of planes as an input.

10. The method of claim 1 , wherein the number of planes is greater than one and the one or more memory blocks comprises a plurality of memory blocks, and wherein the pre-program operation produces a threshold voltage distribution for cells of the plurality of memory blocks that is substantially the same as a threshold voltage distribution produced by a pre-program operation performed for a single plane.

11. A memory circuit, comprising:
at least one charge pump; and
a controller, wherein the controller is configured to:
receive a command indicative of a pre-program operation;
determine a number of planes selected for the pre-program operation;
determine a value for a pre-program time increment parameter based at least in part on the number of planes; and
perform a multi-plane pre-program operation, wherein performing the pre-program operation comprises causing the charge pump to apply a pre-program voltage pulse to memory cells across the selected number of planes for a duration corresponding to a sum of a baseline pre-program pulse duration and the selected value for the pre-program time increment parameter.

12. The memory circuit of claim 11 , wherein the value of the pre-program time increment parameter is greater than zero.

13. The memory circuit of claim 11 , wherein the pre-program time increment parameter value increases non-linearly with an increase in the number of planes.

14. The memory circuit of claim 11 , wherein the controller is configured to determine the value for the pre-program time increment parameter by:
identifying a predefined association between the pre-program time increment parameter value and the selected number of planes; and
overriding an internal timer value with a new timer value, the new timer value being a sum of a default value representing the baseline pre-program pulse duration and the pre-program time increment parameter value.

15. The memory circuit of claim 11 , wherein the controller is configured to determine the value for the pre-program time increment parameter by identifying a user-selected value for the pre-program time increment parameter.

16. The memory circuit of claim 15 , wherein the user-selected value for the pre-program time increment parameter is selected from a continuous range of values.

17. The memory circuit of claim 15 , wherein the user-selected value for the pre-program time increment parameter is selected from a discrete set of values.

18. The memory circuit of claim 17 , wherein the pre-program time increment parameter is a multi-bit parameter, and wherein each value in the discrete set of values corresponds to a respective value of the multi-bit parameter.

19. The memory circuit of claim 11 , wherein the controller is configured to cause the charge pump to apply the pre-program voltage pulse simultaneously to each wordline in a plurality of memory blocks across the selected number of planes.

20. The memory circuit of claim 11 , wherein the pre-program operation produces a threshold voltage distribution for the memory cells that is substantially the same as a threshold voltage distribution produced by a pre-program operation performed for a single plane.

Assignees

• Sandisk Technologies Llc

Inventors

• Pham Long
• Thoppa Sai Gautham

Classifications

• G11C16/102 Primary

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title