Memory device, memory system, method of operating memory device, and method of operating memory system

Patent metadata

Field	Value
Publication number	US-9916900-B2
Application number	US-201615245162-A
Country	US
Kind code	B2
Filing date	Aug 23, 2016
Priority date	Aug 25, 2015
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.

First claim

What is claimed is:

1. A memory device, comprising:
a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and
a control logic configured to generate a pre-programming control signal for pre-programming at least some of the plurality of memory cells before erasing the plurality of memory cells,
wherein the control logic generates the pre-programming control signal by determining application durations of pre-programming voltages or voltage levels of pre-programming voltages respectively supplied to the plurality of word lines while a pre-program operation is being performed, based on respective distances between the substrate and the plurality of word lines.

2. The memory device of claim 1 ,
wherein the control logic is further configured to generate the pre-programming control signal such that a first application duration of a first pre-programming voltage supplied to a first word line of the plurality of word lines adjacent to the substrate is shorter than a second application duration of a second pre-programming voltage supplied to a second word line of the plurality of word lines above the first word line.

3. The memory device of claim 2 ,
wherein when a program/erase cycle count is equal to or greater than a threshold value, the control logic is configured to generate the pre-programming control signal to shorten the first application duration and the second application duration, and
wherein a first amount the first application duration is changed is larger than a second amount the second application duration is changed.

4. The memory device of claim 1 ,
wherein the pre-programming control signal comprises a row address activation times that differ among the plurality of word lines, and
wherein the memory device further comprises a row decoder connected to the memory cell array to select at least some word lines from among the plurality of word lines in response to a row address.

5. The memory device of claim 1 ,
wherein the control logic is further configured to generate the pre-programming control signal such that the application durations of the pre-programming voltages are based on an operating characteristic of the at least some of the plurality of memory cells.

6. The memory device of claim 1 ,
wherein the control logic is further configured to generate the pre-programming control signal such that a first voltage level of a first pre-programming voltage supplied to a first word line of the plurality of word lines adjacent to the substrate is lower than a second voltage level of a second pre-programming voltage supplied to a second word line of the plurality of word lines above the first word line.

7. The memory device of claim 6 ,
wherein when a program/erase cycle count is equal to or greater than a threshold value, the control logic is configured to generate the pre-programming control signal to lower the first and second voltage levels, and
wherein a first amount the first voltage level is changed is larger than a second amount the second voltage level is changed.

8. The memory device of claim 1 ,
wherein the pre-programming control signal comprises a voltage control signal having voltage levels that differ among the word lines, and
wherein the memory device further comprises a voltage generator configured to generate, in response to the voltage control signal, a plurality of pre-programming voltages having different voltage levels.

9. The memory device of claim 1 ,
wherein the control logic is further configured to generate a soft-programming control signal based on an operating characteristic of the at least some of the plurality of memory cells.

10. The memory device of claim 9 ,
wherein the control logic is further configured to generate the soft-programming control signal based on the pre-programming control signal.

11. The memory device of claim 1 ,
wherein a plurality of memory cells of a first NAND string of the plurality of NAND strings vary among the NAND strings has structural variations, and
wherein operating characteristics of the plurality of memory cells vary based on the structural variations.

12. The memory device of claim 11 ,
wherein a second NAND string of the plurality of NAND strings is disposed on the substrate above the first NAND string, and
wherein the control logic is further configured to generate a pre-programming control signal for a plurality of memory cells of the second NAND string such that pre-programming voltages applied to the plurality of word lines coupled to corresponding memory cells of the first NAND string correspond to pre-programming voltages applied to the plurality of word lines coupled to corresponding memory cells of the second NAND string on a one-to-one basis.

13. A memory system comprising:
a memory device including a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and
a memory controller configured to control the memory device to pre-program at least some of the memory cells before erasing the plurality of memory cells,
wherein the memory controller controls the memory device to determine application durations of pre-programming voltages or voltage levels of pre-programming voltages respectively supplied to the plurality of word lines while a pre-program operation is being performed, based on respective distances between the substrate and the plurality of word lines.

14. The memory system of claim 13 ,
wherein the memory controller is further configured to control the memory device to determine application durations of pre-programming voltages or voltage levels of pre-programming voltages respectively supplied to the plurality of word lines.

15. The memory system of claim 14 ,
wherein the memory controller is further configured to control the memory device such that a first pre-programming voltage is supplied to a first word line of the plurality of word lines adjacent to a substrate for a first application duration and a second pre-programming voltage is supplied to a second word line of the plurality of word lines above the first word line for a second application duration,
wherein the first application duration is shorter than the second application duration and
wherein the first pre-programming voltage is lower than the second pre-programming voltage.

16. The memory system of claim 15 ,
wherein when a program/erase cycle count is equal to or greater than a threshold value the memory controller is further configured to control the memory device such that the first application duration is changed a greater amount than the second application duration is changed and the first pre-programming voltage is changed a larger amount than the second pre-programming voltage is changed.

17. The memory system of claim 13 ,
wherein the memory controller is further configured to control the memory device to soft-program the plurality of memory cells after performing an erase operation, based on an operating characteristic of the plurality of memory cells.

18. The memory system of claim 13 ,
wherein the pre-programming voltages include a first pre-programming voltage supplied to a first word line of the plurality of word lines adjacent to a substrate and a second pre-programming voltage supplied to a second word line of the plurality of word lines above the first word

Assignees

• Kim Yoon
• Kim Dong Chan
• Lee Ji Sang
• Samsung Electronics Co Ltd

Inventors

• Kim Yoon
• Kim Dong-Chan
• Lee Ji-Sang

Classifications

• G11C16/3409

  Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/107

  Programming all cells in an array, sector or block to the same state prior to flash erasing · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title