Secure erase of non-volatile memory

Patent metadata

Field	Value
Publication number	US-9779823-B2
Application number	US-201615195931-A
Country	US
Kind code	B2
Filing date	Jun 28, 2016
Priority date	Jan 6, 2016
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

In a non-volatile memory system, a fast bulk secure erase method for erasing data includes, in response to a secure erase command: applying charge to a portion of non-volatile memory in the non-volatile memory system, and performing an erase operation sufficient to remove charge from the portion of non-volatile memory to below an erase threshold. The applied charge is sufficient to program memory cells in the portion of non-volatile memory to above a pre-erase program threshold.

First claim

What is claimed is:

1. A method of erasing data in a non-volatile memory system, the method comprising:
in response to a secure erase command:
applying charge to a portion of non-volatile memory in the non-volatile memory system; and
performing an erase operation sufficient to remove charge from the portion of non-volatile memory to below an erase threshold;

wherein the applied charge is sufficient to program memory cells in the portion of non-volatile memory to above a pre-erase program threshold; and
wherein:
the memory cells in the portion of non-volatile memory each store one of at least four distinct data values as a cell voltage, wherein the at least four distinct data values correspond to at least four sequential voltage ranges and at least three threshold voltages for distinguishing the at least four distinct data values; and
the pre-erase program threshold is at least as high as a second lowest one of the at least three threshold voltages.

2. The method of claim 1 , wherein applying charge to the portion of non-volatile memory includes applying charge to all programmable memory cells in the portion of non-volatile memory.

3. The method of claim 1 , wherein applying charge to the portion of non-volatile memory includes applying a programming operation to all memory cells in the portion of non-volatile memory.

4. The method of claim 1 , wherein applying charge to the portion of non-volatile memory includes using one or more charge pulses having a cumulative effect sufficient to program the memory cells in the portion of non-volatile memory to above the pre-erase program threshold.

5. The method of claim 1 , wherein applying charge to the portion of non-volatile memory includes programming all programmable memory cells in the portion of non-volatile memory to a non-data state.

6. The method of claim 1 , wherein the pre-erase program threshold is at least as high as a highest one of the at least three threshold voltages.

7. The method of claim 1 , further comprising repeating the method for each of a plurality of non-volatile memory portions to erase data in each of the plurality of non-volatile memory portions.

8. The method of claim 7 , wherein the plurality of non-volatile memory portions includes all non-volatile memory portions containing data from a host system.

9. The method of claim 7 , wherein the plurality of non-volatile memory portions includes non-volatile memory portions other than non-volatile memory portions containing memory metadata.

10. A non-volatile memory system, comprising:
a storage medium;
one or more processors; and
memory storing one or more programs, which when executed by the one or more processors cause the non-volatile memory system to:
in response to a secure erase command:
apply charge to a portion of non-volatile memory in the non-volatile memory system; and
perform an erase operation sufficient to remove charge from the portion of non-volatile memory to below an erase threshold;

wherein the applied charge is sufficient to program memory cells in the portion of non-volatile memory to above a pre-erase program threshold; and
wherein:
the memory cells in the portion of non-volatile memory each store one of at least four distinct data values as a cell voltage, wherein the at least four distinct data values correspond to at least four sequential voltage ranges and at least three threshold voltages for distinguishing the at least four distinct data values; and
the pre-erase program threshold is at least as high as a second lowest one of the at least three threshold voltages.

11. The non-volatile memory system of claim 10 , wherein the one or more processors comprise one or more processors of a storage controller and the one or more programs include a pre-erase program module that applies charge to the portion of non-volatile memory in the non-volatile memory system and a secure erase module that performs an erase operation sufficient to remove charge from the portion of non-volatile memory to below the erase threshold.

12. The non-volatile memory system of claim 10 , wherein applying charge to the portion of non-volatile memory includes applying charge to all programmable memory cells in the portion of non-volatile memory.

13. The non-volatile memory system of claim 10 , wherein applying charge to the portion of non-volatile memory includes applying a programming operation to all memory cells in the portion of non-volatile memory.

14. The non-volatile memory system of claim 10 , wherein applying charge to the portion of non-volatile memory includes using one or more charge pulses having a cumulative effect sufficient to program the memory cells in the portion of non-volatile memory to above the pre-erase program threshold.

15. The non-volatile memory system of claim 10 , wherein applying charge to the portion of non-volatile memory includes programming all programmable memory cells in the portion of non-volatile memory to a non-data state.

16. The non-volatile memory system of claim 10 , wherein the pre-erase program threshold is at least as high as a highest one of the at least three threshold voltages.

17. A non-transitory computer readable storage medium, storing one or more programs configured for execution by one or more processors of a non-volatile memory system, the one or more programs including instructions that when executed by the one or more processors cause the non-volatile memory system to:
in response to a secure erase command:
apply charge to a portion of non-volatile memory in the non-volatile memory system; and
perform an erase operation sufficient to remove charge from the portion of non-volatile memory to below an erase threshold;

wherein the applied charge is sufficient to program memory cells in the portion of non-volatile memory to above a pre-erase program threshold; and
wherein:
the memory cells in the portion of non-volatile memory each store one of at least four distinct data values as a cell voltage, wherein the at least four distinct data values correspond to at least four sequential voltage ranges and at least three threshold voltages for distinguishing the at least four distinct data values; and
the pre-erase program threshold is at least as high as a second lowest one of the at least three threshold voltages.

18. The non-transitory computer readable storage medium of claim 17 , wherein applying charge to the portion of non-volatile memory includes applying charge to all programmable memory cells in the portion of non-volatile memory.

19. The non-transitory computer readable storage medium of claim 17 , wherein applying charge to the portion of non-volatile memory includes applying a programming operation to all memory cells in the portion of non-volatile memory.

20. The non-transitory computer readable storage medium of claim 17 , wherein applying charge to the portion of non-volatile memory includes using one or more charge pulses having a cumulative effect sufficient to program the memory cells in the portion of non-volatile memory to above the pre-erase program threshold.

Assignees

• Sandisk Technologies Llc

Inventors

• Schmier Jacob B
• Ellis Robert W
• Higgins James M

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/22

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title