Semiconductor device

Patent metadata

Field	Value
Publication number	US-11950417-B2
Application number	US-202117172458-A
Country	US
Kind code	B2
Filing date	Feb 10, 2021
Priority date	Jun 25, 2020
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.

First claim

What is claimed is:

1. A semiconductor device comprising:
a lower structure including a substrate, and circuit elements on the substrate;
a pattern structure disposed on the lower structure and including a lower pattern layer, an intermediate pattern layer on the lower pattern layer, and an upper pattern layer on the intermediate pattern layer;
a stack structure including gate layers and interlayer insulating layers alternately stacked on the pattern structure in a vertical direction; and
a vertical memory structure penetrating through the stack structure in the vertical direction and in contact with the pattern structure,
wherein the vertical memory structure includes,
a core region;
a channel layer on a side surface and a bottom surface of the core region;
a data storage structure on an outer side surface and a bottom surface of the channel layer; and
a pad pattern contacting the channel layer, on the core region,
the data storage structure includes a first dielectric layer, a second dielectric layer and a data storage layer between the first dielectric layer and the second dielectric layer,
the first dielectric layer is adjacent to the gate layers and the second dielectric layer is in contact with the channel layer,
an upper end of the data storage layer and an upper end of the second dielectric layer overlap an uppermost gate layer among the gate layers in a first direction perpendicular to the vertical direction, and
the upper end of the data storage layer, the upper end of the second dielectric layer, and a bottom surface of the pad pattern are at a lower level than an upper surface of the uppermost gate layer,

wherein the core region extends into the lower pattern layer while penetrating through the upper pattern layer and the intermediate pattern layer,
the intermediate pattern layer includes a horizontal portion and upper and lower vertical portions connected to the horizontal portion and extending in the vertical direction,
the horizontal portion and the upper and lower vertical portions contact the side surface of the core region, and
an upper end of the upper vertical portion overlaps a lowermost gate layer among the gate layers in the first direction.

2. The semiconductor device of claim 1 , wherein the data storage layer has a lower surface in contact with the upper end of the upper vertical portion, and the lower surface of the data storage layer is positioned, in the vertical direction, at a level higher than a lower surface of the lowermost gate layer.

3. The semiconductor device of claim 1 , wherein the second dielectric layer has a lower surface in contact with the upper end of the upper vertical portion, and the lower surface of the second dielectric layer is positioned, in the vertical direction, at a level higher than a lower surface of the lowermost gate layer.

4. The semiconductor device of claim 1 , further comprising first and second capping insulating layers covering the stack structure;
a contact plug penetrating through the first and second capping insulating layers and connected to the pad pattern; and
a bit line connected to the contact plug.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Wukang
• Park Sejun
• Bang Hyoje
• Lee Jaeduk
• Lee Junghoon

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title