Inter-deck plug in three-dimensional memory device and method for forming the same

Patent metadata

Field	Value
Publication number	US-10892280-B2
Application number	US-202016915939-A
Country	US
Kind code	B2
Filing date	Jun 29, 2020
Priority date	Oct 9, 2018
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

Embodiments of 3D memory devices having an inter-deck plug and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck including interleaved conductor and dielectric layers above the substrate, a second memory deck including interleaved conductor and dielectric layers above the first memory deck, and a first and a second channel structure each extending vertically through the first or second memory deck. The first channel structure includes a first memory film and semiconductor channel along a sidewall of the first channel structure, and an inter-deck plug in an upper portion of the first channel structure and in contact with the first semiconductor channel. A lateral surface of the inter-deck plug is smooth. The second channel structure includes a second memory film and semiconductor channel along a sidewall of the second channel structure. The second semiconductor channel is in contact with the inter-deck plug.

First claim

What is claimed is:

1. A method for forming a three-dimensional (3D) memory device, comprising: forming a first dielectric deck comprising a first plurality of interleaved sacrificial layers and dielectric layers above a substrate; forming a first channel structure extending vertically through the first dielectric deck and comprising a first memory film and a first semiconductor channel; forming (i) an inter-deck plug in an upper portion of the first channel structure and in contact with the first semiconductor channel and (ii) a recess with a stepped portion between a top surface of the inter-deck plug and a top surface of the first dielectric deck; forming an etch stop plug in the recess to cover the top surface of the inter-deck plug; forming a second dielectric deck comprising a second plurality of interleaved sacrificial layers and dielectric layers above the first dielectric deck; forming a first opening extending vertically through the second dielectric deck and ending at the etch stop plug; removing the etch stop plug from the recess to form a channel hole comprising the first opening and the recess; forming a second memory film along a sidewall of the first opening and in the recess of the channel hole; and forming a second semiconductor channel over the second memory film and extending vertically through part of the second memory film in the recess to contact the inter-deck plug.

2. The method of claim 1 , wherein forming the inter-deck plug and the recess comprises:
removing upper portions of the first memory film and the first semiconductor channel;
forming an initial inter-deck plug having a top surface flush with the top surface of the first dielectric deck and a bottom surface below an upper end of the first semiconductor channel; and
removing part of the initial inter-deck plug above the upper end of the first semiconductor channel to form the inter-deck plug and the recess.

3. The method of claim 1 , where a depth of the recess is not greater than two times of a thickness of the second memory film.

4. The method of claim 3 , wherein the depth of the recess is between about 20 nm and about 40 nm.

5. The method of claim 2 , wherein the part of the initial inter-deck plug is removed such that a top surface of the inter-deck plug is flush with an upper end of the first semiconductor channel.

6. The method of claim 1 , wherein a lateral surface of the inter-deck plug is smooth.

7. The method of claim 1 , wherein forming the second memory film comprises subsequently forming a blocking layer, a storage layer, and a tunneling layer along the sidewall of the first opening and in the recess in this order.

8. The method of claim 1 , wherein the second memory film fully fills in the recess.

9. The method of claim 1 , wherein forming the second semiconductor channel comprises forming a second opening through the part of second memory film in the recess.

10. The method of claim 1 , wherein each of the first semiconductor channel, the second semiconductor channel, and the inter-deck plug comprises polysilicon.

11. The method of claim 1 , wherein a diameter of the recess is greater than a diameter of the first opening.

12. A method for forming an inter-deck plug in a three-dimensional (3D) memory device, comprising:
forming a lower channel structure extending vertically through a first plurality of interleaved sacrificial layers and dielectric layers above a substrate;
etching a stepped recess in an upper portion of the lower channel structure;
depositing a semiconductor layer to fill the stepped recess;
etching an etch stop recess in an upper portion of the semiconductor layer to form an inter-deck plug having a smooth lateral surface;
depositing an etch stop layer to fill the etch stop recess;
alternatingly depositing a second plurality of interleaved sacrificial layers and dielectric layers above the etch stop layer and the first plurality of interleaved sacrificial layers and dielectric layers;
etching a first opening through the second plurality of interleaved sacrificial layers and dielectric layers until being stopped by the etch stop layer; and
etching away the etch stop layer from the etch stop recess to expose the inter-deck plug.

13. The method of claim 12 , further comprising:
subsequently depositing an upper blocking layer, an upper storage layer, and an upper tunneling layer along a sidewall of the first opening and in the etch stop recess in this order;
etching a second opening through the part of upper blocking layer, upper storage layer, and upper tunneling layer in the etch stop recess to the inter-deck plug; and
depositing an upper semiconductor channel over the upper tunneling layer and extending vertically through the second opening to contact the inter-deck plug.

14. The method of claim 12 , wherein:
forming the lower channel structure comprises subsequently depositing a lower memory film, a lower semiconductor channel, and a lower filling layer in this order; and
etching the stepped recess comprises etching (i) the lower filling layer and (ii) the lower semiconductor channel and lower memory film to different depths.

15. The method of claim 12 , wherein the etch stop layer comprises a metal.

16. The method of claim 13 , wherein a thickness of the etch stop layer is not greater than two times of a combined thickness of the upper blocking layer, upper storage layer, and upper tunneling layer.

17. The method of claim 16 , wherein the thickness of the etch stop layer is between about 20 nm and about 40 nm.

18. The method of claim 12 , wherein etching the etch stop recess comprises etching the lower semiconductor channel such that an upper end of the lower semiconductor channel is flush with a top surface of the inter-deck plug.

19. The method of claim 13 , wherein the upper blocking layer, upper storage layer, and upper tunneling layer fully fill in the etch stop recess.

20. The method of claim 12 , wherein a diameter of the etch stop recess is greater than a diameter of the first opening.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xu Qianbin
• Yang Haohao
• Wang Enbo
• Zhang Yong
• He Jialan

Classifications

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title