Semiconductor device

Patent metadata

Field	Value
Publication number	US-11948883-B2
Application number	US-202117221191-A
Country	US
Kind code	B2
Filing date	Apr 2, 2021
Priority date	Aug 27, 2020
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer; and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a transistor on a substrate;
an interlayer insulating layer on the transistor;
a first metal-containing layer on the interlayer insulating layer; and
a second metal-containing layer on the first metal-containing layer,
wherein:
the second metal-containing layer includes a resistor,
the resistor includes:
a first insulating layer on the first metal-containing layer;
a resistor metal layer on the first insulating layer; and
a second insulating layer on the resistor metal layer, and

the resistor metal layer includes a curved concave recessed side surface such that a center portion of the side surface of the resistor metal layer extends along a curve and further inwardly in the resistor metal layer than a top portion of the side surface of the resistor metal layer and extends along a curve and further inwardly in the resistor metal layer than a bottom portion of the side surface of the resistor metal layer.

2. The semiconductor device as claimed in claim 1 , wherein a lowermost level of a bottom surface of the resistor metal layer is located at a same level as a lowermost level of a top surface of the first insulating layer.

3. The semiconductor device as claimed in claim 1 , wherein a ratio of a thickness of the first insulating layer to a thickness of the second insulating layer ranges from 0.8 to 1.2.

4. The semiconductor device as claimed in claim 1 , wherein a thickness of the first insulating layer ranges from 100 Å to 150 Å.

5. The semiconductor device as claimed in claim 1 , wherein:
the first metal-containing layer includes a lower interconnection line below the resistor and extending in a first direction,
the second metal-containing layer further includes an upper interconnection line on the resistor and extending in a second direction crossing the first direction,
the upper interconnection line includes:
a first portion vertically overlapped with the resistor metal layer, and
a second portion horizontally offset from the resistor metal layer, and

a bottom surface of the first portion of the upper interconnection line is located at a level higher than a bottom surface of the second portion of the upper interconnection line.

6. The semiconductor device as claimed in claim 5 , wherein a bottom surface of the upper interconnection line has a stepped profile.

7. The semiconductor device as claimed in claim 5 , wherein:
the second metal-containing layer further includes a first via and a second via, which are below the upper interconnection line,
the first via electrically connects the first portion of the upper interconnection line to the resistor metal layer, and
the second via electrically connects the second portion of the upper interconnection line to the lower interconnection line.

8. The semiconductor device as claimed in claim 7 , wherein a top surface of the first via is located at a level higher than a top surface of the second via.

9. The semiconductor device as claimed in claim 1 , wherein:
the second metal-containing layer further includes an etch stop layer on a top surface of the resistor, and
the etch stop layer includes a protruding portion protruding into the concave recessed side surface of the resistor metal layer.

10. The semiconductor device as claimed in claim 9 , wherein the protruding portion vertically overlaps with the second insulating layer.

11. A semiconductor device, comprising:
a transistor on a substrate;
an interlayer insulating layer on the transistor;
a first metal-containing layer on the interlayer insulating layer, the first metal-containing layer including a lower interconnection line; and
a second metal-containing layer on the first metal-containing layer,
wherein:
the second metal-containing layer includes a resistor metal layer and an upper interconnection line on the resistor metal layer,
the resistor metal layer is between the upper interconnection line and the lower interconnection line,
the upper interconnection line includes:
a first portion vertically overlapped with the resistor metal layer, and
a second portion horizontally offset from the resistor metal layer,

a bottom surface of the first portion of the upper interconnection line is located at a level higher than a bottom surface of the second portion of the upper interconnection line, and
the resistor metal layer includes a curved concave recessed side surface such that a center portion of the side surface of the resistor metal layer extends along a curve and further inwardly in the resistor metal layer than a top portion of the side surface of the resistor metal layer and extends along a curve and further inwardly in the resistor metal layer than a bottom portion of the side surface of the resistor metal layer.

12. The semiconductor device as claimed in claim 11 , wherein:
the second metal-containing layer further includes an etch stop layer on the resistor metal layer, and
the etch stop layer includes a protruding portion protruding into the concave recessed side surface of the resistor metal layer.

13. The semiconductor device as claimed in claim 12 , wherein:
the second metal-containing layer further includes a first insulating layer below the resistor metal layer, and
a lowermost level of a bottom surface of the etch stop layer is located at a same level as a lowermost level of a top surface of the first insulating layer.

14. The semiconductor device as claimed in claim 11 , wherein:
the second metal-containing layer further includes a first via and a second via, which are below the upper interconnection line,
the first via electrically connects the first portion of the upper interconnection line to the resistor metal layer,
the second via electrically connects the second portion of the upper interconnection line to the lower interconnection line, and
a top surface of the first via is at a level higher than a top surface of the second via.

15. The semiconductor device as claimed in claim 11 , wherein a bottom surface of the upper interconnection line has a stepped profile.

16. A semiconductor device, comprising:
a substrate including an active region;
a device isolation layer defining active patterns on the active region, the device isolation layer covering a lower side surface of each of the active patterns, an upper portion of each of the active patterns protruding above the device isolation layer;
a pair of source/drain patterns in the upper portion of each of the active patterns;
a channel pattern between the pair of source/drain patterns;
a gate electrode crossing the channel pattern and extending in a first direction;
gate spacers at both sides of the gate electrode and extending in the first direction, along with the gate electrode;
a gate dielectric pattern between the gate electrode and the channel pattern and between the gate electrode and the gate spacer;
a gate capping pattern on a top surface of the gate electrode and extending in the first direction, along with the gate electrode;
a first interlayer insulating layer on the gate capping pattern;
an active contact penetrating the first interlayer insulating layer and being coupled to at least one of the source/drain patterns;
a gate contact penetrating the first interlayer insulating layer and being coupled to the gate electrode;
a first metal-containing layer in a second interlayer insulating layer on the first interlayer insulating layer; and
a second metal-containing layer in a third interlayer insulating layer on the second interlayer insulating layer,
wherein:
the first met

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Seonghun
• You Wookyung
• Lee Kyoungwoo
• Jung Juyoung
• Kim Il Sup
• Kim Chin
• Park Kyoungpil
• Park Jinhyung

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/498 Primary

  Resistive arrangements or effects of, or between, wiring layers · CPC title