Process for thin film capacitor integration

Patent metadata

Field	Value
Publication number	US-11948871-B2
Application number	US-202117325197-A
Country	US
Kind code	B2
Filing date	May 19, 2021
Priority date	Jan 8, 2021
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
a silicon wafer;
a first conductive line having first and second surfaces, wherein the second surface is opposite the first surface, and the first surface of the first conductive line is coupled to the silicon wafer;
a second conductive line having first and second surfaces, wherein the second surface is opposite the first surface, and the first surface of the second conductive line is coupled to the silicon wafer;
a first insulation block having first and second portions, wherein:
the first portion has first and second surfaces, the first surface of the first portion is opposite the second portion of the first surface, and the first surface of the first portion is coupled to the silicon wafer; and
the second portion has first and second surfaces, the first surface of the second portion is opposite the second portion of the second surface, the second portion of the second surface is a continuation of the second surface of the first portion, and the first surface of the second portion is coupled to the second surface of the first conductive line;

a second insulation block laterally spaced from the first insulation block and having third, fourth and fifth portions, wherein:
the third portion has first and second surfaces, the first surface of the third portion is opposite the second surface of the third portion, the first surface of the third portion is coupled to the second surface of the first conductive line;
the fourth portion has first and second surfaces, the first surface of the fourth portion is opposite the second surface of the fourth portion, the second surface of the fourth portion is a continuation of the second surface of the third portion, the first surface of the fourth portion is coupled to the silicon wafer; and
the fifth portion has first and second surfaces, the first surface of the fifth portion is opposite the second surface of the fifth portion, the first surface of the fifth portion is coupled to the second surface of the second conductive line, and the second surface of the fifth portion is a continuation of the second surface of the fourth portion;

a third insulation block laterally spaced from the second insulation block and having sixth, seventh and eighth portions, wherein:
the sixth portion has first and second surfaces, the first surface of the sixth portion is opposite the second surface of the sixth portion, and the first surface of the sixth portion is coupled to the second surface of the second conductive line; and
the seventh portion has first and second surfaces, the first surface of the seventh portion is opposite the second surface of the seventh portion, the second surface of the seventh portion is a continuation of the second surface of the sixth portion, and the first surface of the seventh portion is coupled to the silicon wafer;

a conductive pillar coupled to the second surface of the first conductive line, the second portion, and the third portion, and extending beyond the first and second insulation blocks; and
a conductive adhesive block coupled to the second surface of the second conductive line, the fifth portion and the sixth portion.

2. The IC of claim 1 additionally comprising:
a lead frame having first and second lead frame terminals, wherein the first lead frame terminal is coupled to the first conductive line using a first conductive adhesive; and
a capacitor having first and second capacitor terminals, the first capacitor terminal connected to the second lead frame terminal using a second conductive adhesive, and the second capacitor terminal connected to the second conductive line through the conductive adhesive block.

3. The IC of claim 1 , in which the conductive pillar includes copper.

4. The IC of claim 1 , in which the first, second and third insulation blocks include polyimide.

5. The IC of claim 2 , in which the IC is packaged in a flip chip package.

6. The IC of claim 2 , in which the first lead frame terminal is electrically connected to the silicon wafer through the first conductive line, the conductive pillar and conductive adhesive.

7. The IC of claim 1 additionally comprising:
a lead frame having first, second and third lead frame terminals;
a capacitor having first and second capacitor terminals, the first capacitor terminal connected to the second lead frame terminal using a first conductive adhesive, and the second capacitor terminal connected to the third lead frame terminal using a second conductive adhesive; and
the first lead frame terminal is coupled to the first conductive line using a third conductive adhesive.

8. The IC of claim 7 , in which the capacitor is electrically isolated from the silicon wafer.

9. A method of fabricating an integrated circuit (IC) in a package comprising:
forming first and second conductive lines, each having first and second surfaces, wherein the first surfaces of the first and second conductive lines are directly coupled to a silicon wafer, and having a space between the first and second conductive lines;
applying a first insulation block having first and second portions, wherein the first portion has a first surface directly coupled to the silicon wafer, and the second portion has a first surface directly coupled to the second surface of the first conductive line;
applying a second insulation block having third, fourth and fifth portions, wherein the third portion has a first surface directly coupled to the second surface of the first conductive line, the fourth portion is coupled to the silicon wafer, the first conductive line and the second conductive line, and the fifth portion is directly coupled to the second surface of the second conductive line;
applying a third insulation block having sixth, seventh and eighth portions, wherein the sixth portion is directly coupled to the second surface of the second conductive line, and the seventh portion is directly coupled to the silicon wafer;
forming a conductive pillar that is directly coupled to the second surface of the first conductive line, to the second portion, and to the third portion;
applying a first conductive adhesive to the second surface of the second conductive line filling a space between the second insulation block and the third insulation block;
bonding a first capacitor terminal to a first lead frame terminal using a second conductive adhesive; and
mating a second lead frame terminal to the conductive pillar using a third conductive adhesive, and mating a second capacitor terminal to the second conductive line using the first conductive adhesive.

10. The method of claim 9 , in which the conductive pillar extends beyond the first and second insulation blocks.

11. The method of claim 9 , in which the conductive pillar includes copper.

12. The method of claim 9 , in which the forming the conductive pillar includes using a photolithographic process.

13. The method of claim 9 , including:
prior to the forming the conductive pillar, applying a pillar resist mask to any exposed surfaces of the silicon wafer, the second conductive line and the first and second insulation blocks in areas where the conductive pillar will not be formed; and
removing the pillar resist mask after the conductive pillar is formed.

14. The method of claim 13 , in which the pillar resist mask acts as a mold for the conductive pillar.

15. The method of claim 13 , in which the second capacitor terminal is bonded to a third lead frame terminal using a fourth conductive adhesive.

16. An integrated circuit (IC) comprising:
a silicon wafer having first and second s

Assignees

• Texas Instruments Inc

Inventors

• Cook Benjamin Stassen
• Ramadass Yogesh Kumar
• Pavone Salvatore Frank
• Chowdhury Mahmud Halim

Classifications

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07237

  using a polymer adhesive, e.g. an adhesive based on silicone or epoxy · CPC title