Automatic electrostatic chuck bias compensation during plasma processing

US11948780B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11948780-B2
Application numberUS-202117319013-A
CountryUS
Kind codeB2
Filing dateMay 12, 2021
Priority dateMay 12, 2021
Publication dateApr 2, 2024
Grant dateApr 2, 2024

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Embodiments of the present disclosure relate to a system for pulsed direct-current (DC) biasing and clamping a substrate. In one embodiment, the system includes a plasma chamber having an electrostatic chuck (ESC) for supporting a substrate. An electrode is embedded in the ESC and is electrically coupled to a biasing and clamping network. The biasing and clamping network includes at least a shaped DC pulse voltage source and a clamping network. The clamping network includes a DC source and a diode, and a resistor. The shaped DC pulse voltage source and the clamping network are connected in parallel. The biasing and clamping network automatically maintains a substantially constant clamping voltage, which is a voltage drop across the electrode and the substrate when the substrate is biased with pulsed DC voltage, leading to improved clamping of the substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A plasma processing chamber, comprising: a substrate support assembly, comprising: a substrate supporting surface; a first biasing electrode; a first dielectric layer disposed between the first biasing electrode and the substrate supporting surface; a waveform generator configured to generate a plurality of pulsed voltage waveforms during a first time period and halt generation of the plurality of pulsed voltage waveforms during a second time period; a first power delivery line that electrically couples the waveform generator to the first biasing electrode, wherein the first power delivery line comprises a blocking capacitor; a clamping network coupled to the first power delivery line at a first point between the blocking capacitor and the first biasing electrode, the clamping network comprising: a direct-current (DC) voltage source coupled between the first point and ground; and a blocking resistor coupled between the first point and an output of the DC voltage source; and a controller configured to: receive, during the first time period and the second time period, information within a first electrical signal obtained via a first signal trace coupled to the first point, wherein the information within the first electrical signal obtained during the first time period comprises a portion of a waveform of the plurality of pulsed voltage waveforms that comprises a first voltage level, and wherein the information within the first electrical signal obtained during the second time period comprises a second voltage level; compare the first voltage level with the second voltage level; and control a magnitude of a voltage the DC voltage source supplies to the first point of the first power delivery line based on comparing the first voltage level with the second voltage level. 2. The plasma processing chamber of claim 1 , wherein the substrate support assembly comprises an electrostatic chuck, wherein the electrostatic chuck comprises the first dielectric layer and the first biasing electrode. 3. The plasma processing chamber of claim 1 , wherein the blocking resistor has a resistance greater than 100 kOhms. 4. The plasma processing chamber of claim 1 , wherein the substrate support assembly further comprises: a support base; and a second dielectric layer disposed between the support base and the first biasing electrode; and a radio frequency generator electrically coupled to the support base through a second power delivery line, and configured to establish a radio frequency voltage waveform at the support base. 5. The plasma processing chamber of claim 1 , wherein the first dielectric layer has a thickness of between about 0.1 mm and about 2 mm. 6. The plasma processing chamber of claim 1 , wherein the clamping network is connected in parallel with the waveform generator, and the clamping network further comprises: a first diode coupled in parallel with the blocking resistor between the first point and the DC voltage source, wherein an anode side of the diode is coupled to the first point; a first capacitor coupled between a cathode side of the diode and ground; and a second resistor in series with the DC voltage source is coupled in parallel with the first capacitor. 7. The plasma processing chamber of claim 1 , wherein the substrate support assembly further comprises a second biasing electrode, wherein the first biasing electrode and the second biasing electrode are each selected from a group consisting of an edge control electrode and a chucking pole electrode. 8. A plasma processing chamber, comprising: a substrate support assembly, comprising: a substrate supporting surface; a first electrode; a first dielectric layer disposed between the first electrode and the substrate supporting surface; a waveform generator configured to generate a plurality of pulsed voltage waveforms during a first time period and halt generation of the plurality of pulsed voltage waveforms during a second time period; a first power delivery line that electrically couples the waveform generator to the first electrode, wherein the first power delivery line comprises a blocking capacitor; a clamping network coupled to the first power delivery line at a first point between the blocking capacitor and the first electrode, the clamping network comprising: a direct-current (DC) voltage source coupled between the first point and ground; and a blocking resistor coupled between the first point and the DC voltage source; a first signal trace coupled to the first power delivery line between the blocking capacitor and the first electrode, the first signal trace configured to receive a first electrical signal; and a controller configured to: receive, during the first time period and the second time period, information within the first electrical signal obtained via the first signal trace coupled to the first point, wherein the information within the first electrical signal obtained during the first time period comprises a portion of a waveform of the plurality of pulsed voltage waveforms that comprises a first voltage level, and wherein the information within the first electrical signal obtained during the second time period comprises a second voltage level; compare the first voltage level with the second voltage level; and control a magnitude of a voltage the DC voltage source supplies to the first point of the first power delivery line based on comparing the first voltage level with the second voltage level. 9. The plasma processing chamber of claim 8 , further comprising a diode coupled in parallel with the blocking resistor between the first point and the DC voltage source, wherein an anode side of the diode is coupled to the first point. 10. The plasma processing chamber of claim 8 , wherein the substrate support assembly comprises an electrostatic chuck, wherein the electrostatic chuck comprises the first dielectric layer and the first electrode. 11. The plasma processing chamber of claim 8 , wherein the blocking resistor has a resistance greater than 100 kOhms. 12. The plasma processing chamber of claim 8 , wherein the substrate support assembly further comprises: a support base; and a second dielectric layer disposed between the support base and the first electrode; and a radio frequency generator electrically coupled to the support base through a second power delivery line, and is configured to establish a radio frequency voltage waveform at the support base. 13. The plasma processing chamber of claim 8 , wherein the first dielectric layer has a thickness of between about 0.1 mm and about 2 mm. 14. The plasma processing chamber of claim 8 , wherein the clamping network is connected in parallel with the waveform generator, and the clamping network further comprises: a first diode coupled in parallel with the blocking resistor between the first point and the DC voltage source, wherein an anode side of the diode is coupled to the first point; a first capacitor coupled between a cathode side of the diode and ground; and a second resistor in series with the DC voltage source is coupled in parallel with the first capacitor. 15. The plasma processing chamber of claim 8 , wherein the first electrode comprises an edge control electrode or a chucking pole electrode.

Assignees

Inventors

Classifications

  • using electrostatic chucks · CPC title

  • Details of electrostatic chucks · CPC title

  • Workpiece holder · CPC title

  • Amplitude modulation, includes pulsing · CPC title

  • Relative arrangement or disposition of electrodes; moving means · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11948780B2 cover?
Embodiments of the present disclosure relate to a system for pulsed direct-current (DC) biasing and clamping a substrate. In one embodiment, the system includes a plasma chamber having an electrostatic chuck (ESC) for supporting a substrate. An electrode is embedded in the ESC and is electrically coupled to a biasing and clamping network. The biasing and clamping network includes at least a sha…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H01J37/32715. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 02 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).