Formal verification tool to verify hardware design of memory unit

Patent metadata

Field	Value
Publication number	US-11948652-B2
Application number	US-202217573542-A
Country	US
Kind code	B2
Filing date	Jan 11, 2022
Priority date	Nov 11, 2015
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.

First claim

What is claimed is:

1. A formal verification tool configured to verify operation of an instantiation of a hardware unit for storing data defined in a hardware design, the formal verification tool comprising:
assertion verification logic configured to verify a formal assertion that establishes that, for a read of a symbolic address of the instantiation of the hardware unit that occurs after one or more writes to the symbolic address, read data corresponding to the read of the symbolic address matches write data corresponding to the one or more writes to the symbolic address, wherein the symbolic address is a variable that represents each possible address value of the instantiation of the hardware unit which causes the formal verification tool to assess each of the possible address values.

2. The formal verification tool of claim 1 , further comprising a seen symbolic write register and wherein the formal verification tool is configured to set the seen symbolic write register when a write to the symbolic address of the instantiation of the hardware unit occurs and the write data matches symbolic data.

3. The formal verification tool of claim 2 , further comprising a symbolic read request register and wherein the formal verification tool is configured to set the symbolic read request register when a read of the symbolic address in the instantiation of the hardware unit occurs when the seen symbolic write register is set; and
wherein the assertion verification logic is configured to verify the formal assertion by, in response to determining that the seen symbolic write register is set and the symbolic read request register is set, comparing the read data corresponding to the read of the symbolic address to the symbolic data.

4. The formal verification tool of claim 3 , wherein the assertion verification logic is further configured to output an error message in response to determining that the read data corresponding to the read of the symbolic address does not match the symbolic data.

5. The formal verification tool of claim 3 , further comprising a symbolic mask register, and wherein the formal verification tool is configured to, when a write of the symbolic data to the symbolic address in the instantiation of the hardware unit occurs, record, in the symbolic mask register, which particular bits of a memory block were written to; and
wherein the assertion verification logic is configured to combine each of the read data corresponding to the read of the symbolic address and the symbolic data with the data in the symbolic mask register prior to comparing the read data corresponding to the read of the symbolic address and the symbolic data.

6. The formal verification tool of claim 1 , further comprising:
a symbolic read request register, wherein the formal verification tool is configured to, when a read of the symbolic address in the instantiation of the hardware unit occurs, set the symbolic read request register; and
a last written data register, wherein the formal verification tool is configured to, when a write to the symbolic address in the instantiation of the hardware unit occurs, store write data corresponding to the write to the symbolic address in the last written data register.

7. The formal verification tool of claim 6 , wherein the assertion verification logic is configured to verify the formal assertion by, in response to determining that the symbolic read request register is set, comparing the read data corresponding to the read of the symbolic address to the write data in the last written data register.

8. The formal verification tool of claim 7 , wherein the assertion verification logic is configured to output an error message in response to determining that the read data corresponding to the read of the symbolic address does not match the write data in the last written data register.

9. The formal verification tool of claim 7 , further comprising an initialized register, wherein the formal verification tool is configured to, when a write to the symbolic address in the instantiation of the hardware unit occurs, update the initialized register to indicate which particular bits of a memory block at the symbolic address have been written to at least once.

10. The formal verification tool of claim 9 , wherein the assertion verification logic is configured to combine each of the read data corresponding to the read of the symbolic address and the write data in the last written data register with the data in the initialized register prior to comparing the read data corresponding to the read of the symbolic address and the write data in the last written data register.

11. The formal verification tool of claim 3 , further comprising a seen symbolic read register, wherein the formal verification tool is configured to, when the read data corresponding to a read of the symbolic address has been output, set the seen symbolic read register.

12. The formal verification tool of claim 11 , wherein the assertion verification logic is further configured to perform the comparison only if the seen symbolic read register is set.

13. The formal verification tool of claim 1 , wherein the hardware unit implements one or more of: multiple access ports, partial reads and writes, pipelining, and clock gating.

14. A method of verifying operation of an instantiation of a hardware unit for storing data defined by a hardware design, the method comprising:
verifying operation of the instantiation of the hardware unit, using a formal verification tool, by verifying a formal assertion that establishes that when a read of a symbolic address of the instantiation of the hardware unit occurs after one or more writes to the symbolic address, read data corresponding to the read of the symbolic address matches write data corresponding to the one or more writes to the symbolic address, wherein the symbolic address is a variable that represents each possible address value of the instantiation of the hardware unit which causes the formal verification tool to assess each of the possible address values.

15. The method of claim 14 , further comprising, in response to determining that a write to the symbolic address in the instantiation of the hardware unit has occurred, storing write data corresponding to the write to the symbolic address in a last written data register; and wherein verifying the formal assertion comprises comparing the read data corresponding to the read of the symbolic address to the write data in the last written data register.

16. The method of claim 15 , further comprising, in response to determining that a write to the symbolic address in the instantiation of the hardware unit has occurred, updating an initialized register to indicate which particular bits of a memory block at the symbolic address have been written to at least once; and wherein verifying the formal assertion further comprises, prior to comparing the read data corresponding to the read of the symbolic address to the write data in the last written data register, combining each of the read data corresponding to the read of the symbolic address and the write data in the last written data register with data in the initialized register.

17. The method of claim 15 , further comprising, in response to determining that the read data corresponding to the read of the symbolic address does not match the write data in the last written data register, outputting an error message.

18. The method of claim 14 , further comprising:
in response to determining that a write to the symbolic address in the instantiation of the hardware un

Assignees

• Imagination Tech Ltd

Inventors

• Darbari Ashish
• Singleton Iain

Classifications

• G11C29/38 Primary

  Response verification devices · CPC title

• G06F11/2221 Primary

  to test input/output devices or peripheral units · CPC title

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G06F11/3409

  for performance assessment · CPC title

• G11C29/1201

  comprising I/O circuitry · CPC title