Nanosheet transistor with enhanced bottom isolation

Patent metadata

Field	Value
Publication number	US-11942557-B2
Application number	US-202117246762-A
Country	US
Kind code	B2
Filing date	May 3, 2021
Priority date	May 3, 2021
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

A semiconductor nanosheet device including semiconductor channel layers vertically aligned and stacked one on top of another, separated by a work function metal, and a second layer between two first layers, the second layer and two first layers between the semiconductor channel layers and a substrate. A semiconductor device including a lower first layer, a second layer, and a source drain region between a first set of semiconductor channel layers vertically aligned and stacked one on top of another, and a second set of semiconductor channel layers. A method including forming a stack sacrificial layer, a stack of nanosheet layers, forming a cavity by removing the stack sacrificial layer, and simultaneously forming a first layer on an upper surface of the stack sacrificial layer, on vertical side surfaces of the set of sacrificial gates, and an upper first layer and a lower first layer in a portion of the cavity.

First claim

What is claimed is:

1. A semiconductor nanosheet device comprising:
semiconductor channel layers vertically aligned and stacked one on top of another, the semiconductor channel layers separated by a work function metal; and
a second layer sandwiched between two first layers, the second layer and the two first layers are below the semiconductor channel layers and above a substrate, wherein vertical side surfaces of the semiconductor channel layers are vertically aligned with vertical side surfaces of an upper layer of the two first layers, wherein a combined thickness of the second layer and the two first layers is approximately the same as a thickness of the work function metal between the semiconductor channel layers.

2. The semiconductor nanosheet device according to claim 1 , wherein
the second layer and a lower layer of the two first layers extend vertically beyond the semiconductor nanosheet device.

3. The semiconductor nanosheet device according to claim 2 , further comprising:
source drain regions extending laterally from opposite ends of the semiconductor channel layers, wherein the source drain regions are above the second layer over the substrate.

4. The semiconductor nanosheet device according to claim 1 , further comprising:
inner spacers surrounding both vertical side surfaces of the work function metal, wherein the vertical side surface of the inner spacers are vertically aligned with vertical side surfaces of the semiconductor channel layers, wherein the inner spacers comprise silicon nitride.

5. The semiconductor nanosheet device according to claim 1 , further comprising:
source drain regions extending laterally from opposite ends of the semiconductor channel layers.

6. A semiconductor device comprising:
a lower first layer on a substrate;
a second layer on the lower first layer;
an upper first layer on the second layer; and
a source drain region on the second layer between a first set of semiconductor channel layers vertically aligned and stacked one on top of another separated by a work function metal, and a second set of semiconductor channel layers vertically aligned and stacked one on top of another separated by the work function metal, wherein vertical side surfaces of the semiconductor channel layers are vertically aligned with vertical side surfaces of the upper first layer, in both the first set of semiconductor channel layers and the second set of semiconductor channel layers, wherein a combined thickness of the lower first layer, the second layer and the upper first layer is approximately the same as a thickness of the work function metal between the semiconductor channel layers in both the first set of semiconductor channel layers and the second set of semiconductor channel layers.

7. The semiconductor device according to claim 6 , further comprising:
inner spacers surrounding both side surfaces of the work function metal in both the first set of semiconductor channel layers and the second set of semiconductor channel layers, wherein the vertical side surface of the inner spacers are vertically aligned with the vertical side surfaces of the semiconductor channel layers, wherein the inner spacers comprise silicon nitride.

8. The semiconductor device according to claim 6 ,
wherein the source drain regions are above the second layer on the substrate.

9. A semiconductor nanosheet device comprising:
a stack of isolation layers on top of a substrate, the stack of isolation layers comprising a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked in order one atop another, the first dielectric layer and the third dielectric layer having identical composition;
a stack of semiconductor channel layers directly on the stack of isolation layers and stacked one above another; and
work function metal layers between and separating each semiconductor channel layer of the stack of semiconductor channel layers, wherein a width of the work function metal layers is less than a width of the stack of semiconductor channel layers, wherein vertical side surfaces of the semiconductor channel layers are vertically aligned with vertical side surfaces of the third dielectric layer, wherein a combined thickness of the first dielectric layer, the second dielectric layer and the third dielectric layer is approximately the same as a thickness of the work function metal layers between each semiconductor channel layer of the stack of semiconductor channel layers.

10. The semiconductor nanosheet device according to claim 9 , wherein
the first dielectric layer and the second dielectric layer extend horizontally beyond the stack of semiconductor channel layers.

11. The semiconductor nanosheet device according to claim 10 , further comprising:
source drain regions extending laterally from opposite ends of the semiconductor channel layers, wherein a bottommost surface of the source drain regions directly contacts a topmost surface of the second layer over the substrate.

12. The semiconductor nanosheet device according to claim 10 , further comprising:
inner spacers surrounding both side surfaces of each of the work function metal layers, wherein vertical side surfaces of the inner spacers are vertically aligned with vertical side surfaces of the semiconductor channel layers, wherein the inner spacers comprise silicon nitride.

Assignees

• IBM

Inventors

• Yu Lan
• Greene Andrew M
• Xu Wenyu
• Wu Heng

Classifications

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title