Bulk nanosheet with dielectric isolation

Patent metadata

Field	Value
Publication number	US-10312323-B2
Application number	US-201715651420-A
Country	US
Kind code	B2
Filing date	Jul 17, 2017
Priority date	Oct 21, 2015
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

First claim

What is claimed is:

1. A nanowire field effect transistor (FET) device, comprising:
a bulk semiconductor wafer comprising a dielectric isolation region in a top portion thereof, wherein the dielectric isolation region comprises a thermal oxide;
nanowire stacks on the bulk semiconductor wafer, wherein each of the nanowire stacks comprises alternating layers of a sacrificial material and a channel material, wherein portions of the channel material are released from the nanowire stacks in a channel region of the FET device and comprise nanowire channels of the FET device, and wherein a first layer in the nanowire stacks comprises the sacrificial material and is present on the bulk semiconductor wafer; and
a gate surrounding the nanowire channels in the channel region of the device, wherein the first layer in the nanowire stacks has an inverted triangular shape beneath the gate in the channel region of the device.

2. The nanowire FET device of claim 1 , wherein the gate completely surrounds one or more of the nanowire channels in a gate-all-around configuration.

3. The nanowire FET device of claim 1 , further comprising:
at least one dopant implanted into the top portion of the bulk semiconductor wafer.

4. The nanowire FET device of claim 3 , wherein the at least one dopant is selected from the group consisting of: fluorine, phosphorous, and combinations thereof.

5. The nanowire FET device of claim 3 , wherein the at least one dopant is implanted into the top portion of the bulk semiconductor wafer at a dose of from about from about 5×10 15 atoms/cm 2 to about 5×10 16 atoms/cm 2 , and ranges therebetween.

6. The nanowire FET device of claim 3 , wherein the bulk semiconductor wafer has a thickness of from about 0.1 millimeters to about 0.75 millimeters, and ranges therebetween.

7. The nanowire FET device of claim 3 , wherein the top portion of the bulk semiconductor wafer comprises a first thickness of from about 100 angstroms to about 500 angstroms, and ranges therebetween, of the bulk semiconductor wafer.

8. The nanowire FET device of claim 1 , wherein the sacrificial material comprises silicon germanium and the channel material comprises silicon.

9. The nanowire FET device of claim 1 , wherein the sacrificial material comprises silicon and the channel material comprises silicon germanium.

10. The nanowire FET device of claim 1 , wherein the first layer in the nanowire stacks present on the bulk semiconductor wafer is thicker than other layers in the nanowire stacks.

11. The nanowire FET device of claim 10 , wherein the first layer in the nanowire stacks has a thickness of from about 20 nanometers to about 35 nanometers, and ranges therebetween.

12. The nanowire FET device of claim 10 , wherein the other layers in the nanowire stacks have a thickness of from about 10 nanometers to about 25 nanometers, and ranges therebetween.

13. The nanowire FET device of claim 1 , further comprising:
spacers on opposite sides of the gate.

14. The nanowire FET device of claim 13 , wherein the spacers offset the gate from source and drain regions of the device which comprise portions of the nanowire stacks extending out from the gate.

15. The nanowire FET device of claim 14 , wherein the source and drain regions of the device comprise an in-situ doped epitaxial material selected from the group consisting of: silicon, silicon carbide, and silicon germanium.

16. The nanowire FET device of claim 1 , wherein the gate is a metal gate.

17. The nanowire FET device of claim 1 , further comprising:
a gate dielectric separating the gate from the nanowire channels, wherein the gate dielectric is selected from the group consisting of: hafnium oxide and lanthanum oxide.

18. The nanowire FET device of claim 1 , wherein the bulk semiconductor wafer comprises a material selected from the group consisting of: silicon, strained silicon, silicon carbide, germanium, silicon germanium, silicon-germanium-carbon, a silicon alloy, a germanium alloy, gallium arsenide, indium arsenide, indium phosphide, and combinations thereof.

19. The nanowire FET device of claim 1 , wherein the dielectric isolation region is continuous along the top portion of the bulk semiconductor wafer beneath the nanowire stacks.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Doris Bruce B
• Wang Junli

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/0125

  comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10W10/012

  using local oxidation of silicon [LOCOS] · CPC title