Electronic devices in semiconductor package cavities

Patent metadata

Field	Value
Publication number	US-11942386-B2
Application number	US-202017001429-A
Country	US
Kind code	B2
Filing date	Aug 24, 2020
Priority date	Aug 24, 2020
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor package including a mold compound covering a semiconductor die, the semiconductor package having a surface and a cavity in the surface, the semiconductor die having a device side facing the cavity, the device side having circuitry therein; and
an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound, the conductive terminal having a first end physically contacting the device side and a second end extending into the cavity, and wherein the conductive terminal comprises a copper post, and wherein the electronic device includes another semiconductor die.

2. The semiconductor device of claim 1 , wherein the conductive terminal extends into the cavity via a bottom surface of the cavity, and wherein the cavity is uncovered.

3. The semiconductor device of claim 1 , further comprising a tin silver plating on an end of the copper post distal to the semiconductor package.

4. The semiconductor device of claim 2 , wherein the conductive terminal comprises a solder ball.

5. The semiconductor device of claim 1 , wherein the electronic device comprises a passive electronic device.

6. The semiconductor device of claim 1 , further comprising a redistribution layer (RDL) between the semiconductor die and the surface of the semiconductor package.

7. The semiconductor device of claim 6 , wherein the RDL comprises a copper layer plated with a nickel palladium layer or a nickel tungsten layer.

8. The semiconductor device of claim 6 , wherein the RDL abuts one of a polyimide coat and a polybenzoxazole layer.

9. A semiconductor device, comprising:
a semiconductor die;
a die pad supporting the semiconductor die;
a mold compound covering the semiconductor die and the die pad, the semiconductor die positioned between the die pad and a surface of the mold compound, a cavity in the surface of the mold compound;
a conductive terminal physically contacting a bond pad of the semiconductor die, the conductive terminal extending through the surface of the mold compound and into the cavity; and
an electronic device including another semiconductor die, the electronic device placed in the cavity and coupled to the conductive terminal.

10. The semiconductor device of claim 9 , wherein the conductive terminal comprises a metal post.

11. The semiconductor device of claim 9 , wherein the conductive terminal comprises a solder ball.

12. The semiconductor device of claim 9 , further comprising multiple electronic devices positioned in the cavity and coupled to the conductive terminal.

13. The semiconductor device of claim 12 , wherein the multiple electronic devices are positioned entirely inside the cavity such that the multiple electronic devices do not extend beyond a plane of the surface of the mold compound.

14. The semiconductor device of claim 9 , wherein the conductive terminal couples to the semiconductor die via a redistribution layer.

15. The semiconductor device of claim 14 , wherein the redistribution layer comprises a metal layer coupled to a plating layer.

16. A semiconductor device, comprising:
a semiconductor die;
a redistribution layer (RDL) coupled to the semiconductor die, the redistribution layer including bond pads of the semiconductor die;
first and second conductive terminals physically contacting a respective one of the bond pads;
a mold compound covering the semiconductor die and the redistribution layer, the mold compound including a cavity, wherein top surfaces of the first and second conductive terminals are positioned between the RDL and a bottom surface of the cavity;
a first electronic device coupled to the first conductive terminal and positioned inside the cavity; and
a second electronic device coupled to the second conductive terminal and positioned inside the cavity.

17. The semiconductor device of claim 16 , wherein each of the first and second conductive terminals is selected from the group consisting of: a copper post plated with a tin silver layer, and a solder ball coupled to a copper layer plated with a nickel palladium layer or a nickel tungsten layer.

Assignees

• Texas Instruments Inc

Inventors

• Manack Christopher Daniel
• Thompson Patrick Francis
• Chen Qiao

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/859

  Bump connectors and bond wires · CPC title