Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus

Patent metadata

Field	Value
Publication number	US-11937429-B2
Application number	US-202117556704-A
Country	US
Kind code	B2
Filing date	Dec 20, 2021
Priority date	Apr 19, 2016
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

First claim

We claim:

1. A method of forming an integrated structure, comprising:
forming a vertical stack comprising first levels alternating with second levels, the first levels comprising a nitride material and the second levels comprising a dielectric material, an uppermost level of the stack being one of the first levels;
forming an insulative material over the uppermost level of the stack;
forming an etch-resistant material over the insulative material, the etch resistant material comprising silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus, the material being in direct physical contact with the insulative material;
forming an opening extending through the etch resistant material, through the insulative material, and through at least some of the first and second levels;
removing the nitride material of the first levels without removing a remaining region of the etch-resistant material; and
replacing the nitride material with conductive material.

2. The method of claim 1 wherein said one or more substances include carbon.

3. The method of claim 1 wherein said one or more substances include oxygen.

4. The method of claim 1 wherein said one or more substances include boron.

5. The method of claim 1 wherein said one or more substances include phosphorus.

6. The method of claim 1 wherein said vertical stack is part of a NAND memory array.

7. The method of claim 6 wherein the etch-resistant material extends across memory cells of the NAND memory array.

8. A method of forming an integrated structure, comprising:
forming a vertically-stack of levels of dielectric material alternating with levels of sacrificial material, an uppermost level of the stack comprising the sacrificial material;
forming an insulative region over the uppermost level;
forming a silicon nitride material over and directly against the insulative region, the material comprising silicon and nitrogen;
forming an opening extending through the silicon nitride material, through the insulative region and through at least some of the levels of sacrificial material;
replacing the sacrificial material with a conductive material to form conductive levels with retention of remaining regions of the silicon nitride material; and
forming channel material within the opening.

9. The method of claim 8 wherein the channel material is formed within the opening to extend along the conductive levels, the levels of dielectric material, the insulative region and the silicon nitride material.

10. The method of claim 8 wherein the silicon nitride material further comprises one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus, a total concentration of said one or more substances being present within a range of from about 2 atomic percent to about 20 atomic percent.

11. The method of claim 10 wherein said total concentration of the one or more substances is at least about 4 atomic percent.

12. The method of claim 8 further comprising forming a secondary opening extending through the silicon nitride material and into the stack, the secondary opening being spaced from the opening by an expanse of the stack.

13. A method of forming an integrated structure, comprising:
forming a vertically-stack comprising conductive levels alternating with dielectric levels;
forming vertically-stacked NAND memory cells along the conductive levels within a memory array region;
forming a silicon nitride material over the memory array region, the silicon nitride material being separated by an uppermost of the conductive levels by an intervening insulative material; the silicon nitride material comprising silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus;
forming a first opening within the memory array region extending through the silicon nitride material over the memory array region and through at least some of the vertically-stacked conductive levels;
forming a channel material within the first opening; and
forming a second opening spaced from the first opening by regions of the stack, the second opening having sidewalls comprising the silicon nitride material, the insulative material, conductive material of the conductive levels and dielectric material of the dielectric levels, the second opening subdividing the memory array region into programmable blocks.

14. The method of claim 13 wherein said total concentration of the one or more substances is within a range of from about 6 atomic percent to about 11 atomic percent.

15. The method of claim 13 wherein said one or more substances include carbon.

16. The method of claim 13 wherein said one or more substances include oxygen.

17. The method of claim 13 wherein said one or more substances include boron.

18. The method of claim 13 wherein said one or more substances include phosphorus.

Assignees

• Micron Technology Inc

Inventors

• Dorhout Justin B
• Wang Fei
• Carter Chet E
• Laboriante Ian
• Hopkins John D
• Shrotri Kunal
• Meyer Ryan
• Shamanna Vinayak
• Parekh Kunal R
• Roberts Martin C
• Park Matthew

Classifications

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H01L23/528

  Electricity · mapped topic

• H01L23/53257

  Electricity · mapped topic