Semiconductor memory device
US-2024334693-A1 · Oct 3, 2024 · US
Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
US8946076B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8946076-B2 |
| Application number | US-201313835551-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 15, 2013 |
| Priority date | Mar 15, 2013 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
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Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation material. Three zones occur during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner. Cavities are formed to extend into the electrically conductive levels along sidewalls of the opening. Charge blocking dielectric and charge-storage structures are formed within the cavities.
First claim
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We claim: 1. A method of fabricating integrated structures, comprising: forming an opening to extend partially through a stack of alternating first and second levels; forming a liner along sidewalls of the opening; extending the opening into the stack utilizing etching conditions that penetrate the first and second levels and that remove at least a majority of the liner; and wherein the first and second levels comprise silicon dioxide and conductively-doped silicon, respecti…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8946076B2 cover?
- Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation …
- Who is the assignee on this patent?
- Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D30/0411. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).