Semiconductor package

Patent metadata

Field	Value
Publication number	US-11935847-B2
Application number	US-202217737472-A
Country	US
Kind code	B2
Filing date	May 5, 2022
Priority date	Mar 27, 2019
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

A semiconductor package includes: a connection structure having a first surface and a second, and including a redistribution layer; a passive component disposed on the first surface of the connection structure, and electrically connected to the redistribution layer; a semiconductor chip disposed on the first surface of the connection structure, and electrically connected to the redistribution layer; a first encapsulant disposed on the first surface of the connection structure and covering at least a portion of the semiconductor chip; a second encapsulant disposed on the first surface of the connection structure and covering at least a portion of the passive component; an antenna substrate disposed on the first encapsulant and including a wiring layer, at least a portion of the wiring layer including an antenna pattern; and a through via penetrating at least a portion of each of the connection structure, the first encapsulant, and the antenna substrate.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a connection structure having a first surface and a second surface opposing the first surface, and comprising one or more redistribution layers;
one or more passive components disposed on the first surface of the connection structure, and electrically connected to the one or more redistribution layers of the connection structure;
a semiconductor chip disposed on the first surface of the connection structure, and electrically connected to the one or more redistribution layers of the connection structure;
a first encapsulant disposed on the first surface of the connection structure and covering at least a portion of the semiconductor chip;
a second encapsulant disposed on the first surface of the connection structure and covering at least a portion of the one or more passive components;
an antenna substrate disposed on the first encapsulant and comprising one or more wiring layers, at least a portion of the one or more wiring layers comprising an antenna pattern; and
a through via penetrating at least a portion of each of the connection structure, the first encapsulant, and the antenna substrate,
wherein the second encapsulant is spaced apart from a side surface of the semiconductor chip,
wherein a portion of the second encapsulant is on a side surface of the one or more passive components that faces towards the side surface of the semiconductor chip, and
wherein the first encapsulant fills between the portion of the second encapsulant, on the side surface of the one or more passive components, and the side surface of the semiconductor chip.

2. The semiconductor package of claim 1 , wherein the antenna substrate is in physical contact with an upper surface of the first encapsulant.

3. The semiconductor package of claim 1 , wherein an upper surface of the second encapsulant is covered with the first encapsulant, the upper surface of the second encapsulant and the first surface of the connection structure facing in a same direction.

4. The semiconductor package of claim 1 , wherein a surface of the semiconductor chip on which connection pads are disposed faces the first surface of the connection structure and is in contact with the connection structure.

5. The semiconductor package of claim 4 , wherein the surface of the semiconductor chip in contact with the connection structure has a step with respect to a surface of the one or more passive components faces the first surface of the connection structure.

6. The semiconductor package of claim 1 , further comprising a wiring member disposed between the connection structure and the one or more passive components, and comprising one or more wiring layers electrically connecting the one or more passive components to the one or more redistribution layers of the connection structure.

7. The semiconductor package of claim 1 , wherein the through via further penetrates at least portion of the second encapsulant.

8. The semiconductor package of claim 1 , further comprising:
a passivation layer disposed on the second surface of the connection structure and covering at least portions of the one or more redistribution layers; and
an electrical connection metal disposed on a lower surface of the passivation layer.

9. The semiconductor package of claim 8 , wherein the through via further penetrates the passivation layer, thereby electrically connecting the one or more wiring layers of the antenna substrate and the electrical connection metal to each other.

10. The semiconductor package of claim 1 , wherein the antenna substrate comprises:
a core layer,
a first wiring layer and a second wiring layer disposed on a lower surface of the core layer and an upper surface of the core layer, respectively,
a plurality of first build-up insulating layers disposed on the lower surface of the core layer,
a plurality of third wiring layers, each disposed on a lower surface of each of the plurality of first build-up insulating layers,
a plurality of second build-up insulating layers disposed on the upper surface of the core layer,
a plurality of fourth wiring layers, each disposed on an upper surface of each of the plurality of second build-up insulating layers,
a first cover layer disposed on the lower surface of a lowermost first build-up insulating layer among the plurality of first build-up insulating layers, and covering at least portions of a lowermost third wiring layer among the plurality of third wiring layers,
a second cover layer disposed on the upper surface of an uppermost second build-up insulating layer among the plurality of second build-up insulating layers, and covering at least portions of an uppermost fourth wiring layer among the plurality of fourth wiring layers,
wherein the core layer is thicker than each of the plurality of first build-up insulating layers and the plurality of second build-up insulating layers.

11. The semiconductor package of claim 10 , wherein the through via penetrates the first cover layer and is electrically connected to the lowermost third wiring layer among the plurality of third wiring layers.

12. The semiconductor package of claim 10 , wherein
the uppermost fourth wiring layer among the plurality of fourth wiring layers comprises a first antenna pattern,
the second wiring layer comprises a second antenna pattern disposed on a lower level than the first antenna pattern,
at least one of the first wiring layer and the plurality of third wiring layers comprises a feeding pattern electrically connected to the second antenna pattern, and
at least one of the plurality of fourth wiring layers, the first wiring layer, the second wiring layer, and the plurality of third wiring layers comprises a ground pattern.

13. A semiconductor package, comprising:
a connection structure having a first surface and a second surface opposing the first surface, and comprising one or more redistribution layers;
one or more passive components disposed on the first surface of the connection structure, and electrically connected to the one or more redistribution layers of the connection structure;
a semiconductor chip disposed on the first surface of the connection structure, and electrically connected to the one or more redistribution layers of the connection structure;
an encapsulant disposed on the first surface of the connection structure and covering at least a portion of the semiconductor chip;
an antenna substrate disposed on the encapsulant and comprising one or more wiring layers, at least a portion of the one or more wiring layers comprising an antenna pattern; and
a through via penetrating at least a portion of each of the connection structure, the encapsulant, and the antenna substrate,
wherein a surface of the semiconductor chip to which connection pads and the one or more redistribution layers are connected faces the first surface of the connection structure in a first direction,
wherein a surface of the one or more passive components to which electrodes and the one or more redistribution layers are connected faces the first surface of the connection structure in the first direction,
wherein the surface of the semiconductor chip is farther in the first direction than the surface of the one or more passive components,
wherein the semiconductor package further comprises an additional encapsulant disposed on the first surface of the connection structure and covering at least a portion of the one or more passive components,
wherein the additional encapsulant is spaced apart from a side surface of the semiconductor chip,
wherein a portion of the additional encapsulant is on a side surface of the one or more p

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Myungsam
• Lee Changbae
• Cho Bongju
• Ko Younggwan
• Lee Yongkoon
• Kim Moonil
• Ko Youngchan

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W44/248

  for antennas · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W72/90

  Bond pads, in general · CPC title