Integrated circuit structure with backside dielectric layer having air gap

Patent metadata

Field	Value
Publication number	US-11935781-B2
Application number	US-202217815669-A
Country	US
Kind code	B2
Filing date	Jul 28, 2022
Priority date	Apr 29, 2020
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
etching a recess in a substrate, wherein the substrate comprises a first material;
forming a plug in the recess in the substrate, wherein the plug comprises a second material different than the first material;
forming an epitaxial structure over the plug;
forming a gate structure on a first side of the substrate adjacent epitaxial structure;
removing at least a portion of a backside of the substrate to expose the plug;
forming a dielectric layer over the plug, the dielectric layer having an air gap therein;
removing the plug to form a backside via opening through the dielectric layer; and
forming a backside via in the backside via opening, wherein the backside via is electrically coupled to the epitaxial structure.

2. The method of claim 1 , wherein forming the plug comprises epitaxially growing the second material, wherein the second material is a semiconductor material.

3. The method of claim 2 , wherein the semiconductor material is silicon germanium.

4. The method of claim 3 , wherein the semiconductor material is free of n-type dopants and p-type dopants.

5. The method of claim 3 , wherein the semiconductor material comprises a first silicon germanium layer and a second silicon germanium layer, wherein the first silicon germanium layer has a different germanium concentration than the second silicon germanium layer.

6. The method of claim 5 , wherein the first silicon germanium layer has a germanium atomic percentage in a range between 20% and 50%, wherein the second silicon germanium layer has a germanium atomic percentage in a range between 5% and 20%.

7. The method of claim 1 , wherein the epitaxial structure is a source region or a drain region.

8. A method of forming a semiconductor device, the method comprising:
forming a plurality of first channel layers over a substrate;
forming a first recess in the substrate adjacent the plurality of first channel layers;
forming a plug in the first recess;
forming an epitaxial structure over the plug, the epitaxial structure extending along sidewalls of the plurality of first channel layers;
forming a first gate structure surrounding one or more of the plurality of first channel layers;
forming a front-side interconnection structure on a front-side of the substrate;
removing at least a portion of the substrate along sidewalls of the plug;
forming a dielectric layer along sidewalls of the plug;
removing at least a portion of the plug to form a second recess in the dielectric layer; and
forming a first backside via in the second recess, wherein the first backside via is electrically connected to the epitaxial structure.

9. The method of claim 8 , wherein forming the plug comprises:
forming a first layer; and
forming a second layer over the first layer, wherein during removing the plug, the second layer has a different etch rate than the first layer.

10. The method of claim 8 , wherein the dielectric layer contacts the first gate structure.

11. The method of claim 8 , wherein forming the dielectric layer forms a void in the dielectric layer.

12. The method of claim 11 , further comprising after forming the first backside via, forming a backside interconnection structure on the dielectric layer, wherein the void remains in the dielectric layer after forming the backside interconnection structure.

13. The method of claim 8 , wherein forming the plug comprises performing a cyclic deposition-etch process.

14. The method of claim 8 , wherein forming the plug comprises a selective epitaxial growth (SEG) process having a higher growth rate along a crystal plane of a bottom of the first recess than along a crystal plane of the first channel layers.

15. An integrated circuit (IC) structure comprising:
a gate structure;
a first epitaxial structure on a first side of the gate structure;
a second epitaxial structure on a second side of the gate structure;
a front-side interconnection structure on a front-side of the first epitaxial structure and a front-side of the second epitaxial structure;
a backside dielectric layer, wherein the gate structure, the first epitaxial structure, and the second epitaxial structure are between the backside dielectric layer and the front-side interconnection structure; and
a backside via extending through the backside dielectric layer, the backside via being electrically connected to the first epitaxial structure, wherein the backside dielectric layer extends continuously from the backside via to under the second epitaxial structure.

16. The IC structure of claim 15 , further comprising a void in the backside dielectric layer.

17. The IC structure of claim 16 , wherein the void laterally overlaps the second epitaxial structure.

18. The IC structure of claim 15 , wherein a width of the backside via in a cross-sectional view decreases as the backside via extends away from the first epitaxial structure.

19. The IC structure of claim 15 , further comprising a silicide region between the backside via and the first epitaxial structure.

20. The IC structure of claim 19 , wherein the second epitaxial structure is free of a silicide region on a surface facing the backside dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Lun
• Lee Wei-Yang
• Lin Chia-Pin
• Peng Yuan-Ching

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title