Memory cells and methods of forming a capacitor including current leakage paths having different total resistances

Patent metadata

Field	Value
Publication number	US-11935574-B2
Application number	US-202117496564-A
Country	US
Kind code	B2
Filing date	Oct 7, 2021
Priority date	Jul 10, 2019
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

First claim

The invention claimed is:

1. A method of forming a capacitor, comprising:
forming a conductive lining in a capacitor opening in insulative-comprising material to comprise a first capacitor electrode of a capacitor being formed in the capacitor opening and forming sacrificial material laterally-inward of the conductive lining;
vertically recessing the conductive lining and the sacrificial material in the capacitor opening relative to a top surface of the insulative-comprising material immediately-laterally-adjacent the capacitor opening;
forming a leaker-material lining in the capacitor opening atop the conductive lining;
after forming the leaker-material lining, removing remaining of the sacrificial material from being laterally-inward of the conductive lining in the capacitor opening;
after removing the sacrificial material, forming capacitor insulator material in the capacitor opening aside the conductive lining and the leaker-material lining;
forming conductive material in the capacitor opening to comprise a second capacitor electrode of the capacitor; and
the capacitor comprising an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material, the leaker-material lining forming a parallel current leakage path that is circuit-parallel with the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path.

2. The method of claim 1 wherein the vertically recessing of the conductive lining and the sacrificial material in the capacitor opening occurs at the same time.

3. The method of claim 1 wherein the vertically recessing of the conductive lining and the sacrificial material in the capacitor opening occurs at different time-spaced periods of time.

4. The method of claim 1 wherein the vertically recessing of the conductive lining and the sacrificial material in the capacitor opening widens the capacitor opening in the insulative-comprising material above the conductive lining.

5. The method of claim 1 wherein the leaker-material lining is formed in the capacitor opening atop the sacrificial material.

6. The method of claim 5 wherein the leaker-material lining is formed in the capacitor opening directly against the sacrificial material.

7. The method of claim 1 comprising forming the leaker-material lining to be everywhere laterally-outward of laterally-innermost surfaces of the first capacitor electrode.

8. The method of claim 1 comprising forming at least some of the leaker-material lining to be laterally-outward of laterally-outermost surfaces of the first capacitor electrode.

9. The method of claim 1 comprising forming the leaker-material lining to have maximum lateral thickness above individual of the laterally-spaced walls of the first capacitor electrode that is less than maximum lateral thickness of the capacitor insulator material above the individual laterally-spaced walls of the first capacitor electrode.

10. The method of claim 1 comprising forming the leaker-material lining to be directly above less than all of the topmost surfaces of the laterally-spaced walls of the first capacitor electrode.

11. The method of claim 1 comprising forming the leaker-material lining to not be directly above a topmost surface of the capacitor insulator material.

12. The method of claim 1 comprising forming the leaker-material lining to not be directly against any lateral sidewall surface of the second capacitor electrode.

13. A method of forming an array of capacitors, comprising:
forming a conductive lining in individual capacitor openings in insulative-comprising material in first and second areas of a substrate to comprise first capacitor electrodes of capacitors being formed in the capacitor openings and forming sacrificial material laterally-inward of the conductive linings;
vertically recessing the conductive linings and the sacrificial material in the capacitor openings in the first and second areas relative to respective top surfaces of the insulative-comprising material immediately-laterally-adjacent the capacitor openings;
forming a leaker-material lining in the capacitor openings in the first and second areas atop the conductive linings;
removing the leaker-material linings from the capacitor openings in the second area to leave the leaker-material linings in the capacitor openings in the first area;
after removing the leaker-material linings from the second area, removing remaining of the sacrificial material from being laterally-inward of the conductive linings in the capacitor openings in the first and second areas;
after removing the sacrificial material, forming capacitor insulator material in the capacitor openings in the first and second areas aside the conductive linings and the leaker-material linings;
forming conductive material in the capacitor openings in the first and second areas to comprise second capacitor electrodes of the capacitors; and
the capacitors individually comprising an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material, individual of the leaker-material linings forming a parallel current leakage path that is circuit-parallel with the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path.

Assignees

• Micron Technology Inc

Inventors

• Mutch Michael
• Chavan Ashonita A
• Chhajed Sameer
• Cook Beth R
• Muthukrishnan Kamal Kumar
• Ramaswamy Durai Vishak Nirmal
• Williamson Lance

Classifications

• H10D1/692

  Electrodes · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10D1/68

  Capacitors having no potential barriers · CPC title

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title