Memory programming methods and memory systems

Patent metadata

Field	Value
Publication number	US-9773551-B2
Application number	US-201614987630-A
Country	US
Kind code	B2
Filing date	Jan 4, 2016
Priority date	Oct 23, 2012
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

First claim

The invention claimed is:

1. A memory programming method comprising:
first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state;
after the first applying, determining that the memory cell failed to place in the desired state;
after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state; and
after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state.

2. The method of claim 1 further comprising:
repeating the determining, the second applying, and the third applying;
verifying that the memory cell has been programmed to the desired state after one of the third applyings; and
ceasing the repeating as a result of the verifying.

3. The method of claim 1 wherein the first and third signals have a common polarity and the second signal has a polarity opposite to the common polarity of the first and third signals.

4. The method of claim 1 wherein the third signal has a characteristic which is different than the first signal.

5. The method of claim 1 wherein the first applying comprises applying the first signal to the memory cell and a plurality of additional memory cells, and further comprising:
determining that the additional memory cells placed in the desired state; and
isolating the additional memory cells from the second and third signals during the second and third applyings as a result of the determining that the additional memory cells placed in the desired state.

6. The method of claim 1 wherein the memory cell has different resistances corresponding to the desired and different states, and wherein the third applying changes the resistance of the memory cell from a first resistance value to a second resistance value which corresponds to the desired state.

7. The method of claim 1 wherein the first, second and third applyings comprise applying respective ones of the first, second and third signals across terminals of the memory cells to change a resistance of a memory element intermediate the terminals.

8. The method of claim 1 wherein the second signal provides the memory cell in a state which is different than the desired state.

9. A memory programming method comprising:
accessing an instruction to program a memory cell to a desired state corresponding to a desired value of digital information; and
as a result of the accessing, applying a plurality of different signals to the memory cell to program the memory cell to the desired state including applying a plurality of signals which correspond to the desired state and applying at least one of the signals which corresponds to another state which is different than the desired state.

10. The method of claim 9 wherein the applying the different signals comprises applying to implement a single write operation with respect to the memory cell to program the memory cell to the desired state.

11. The method of claim 9 wherein the applying the different signals changes the resistance of the memory cell.

12. The method of claim 9 wherein the signals which correspond to the desired state have a common polarity and the at least one signal has a polarity opposite to the common polarity.

13. The method of claim 9 wherein the applying comprises:
first applying one of the signals which corresponds to the desired state;
after the first applying, second applying the at least one of the signals which corresponds to the another state; and
third applying another of the signals which corresponds to the desired state after the second applying.

14. The method of claim 9 wherein the applying the at least one of the signals which corresponds to the another state provides the memory cell in the another state.

15. A memory programming method comprising:
accessing an instruction to program a memory cell to a desired one of a plurality of different states which correspond to different values of digital information, wherein the memory cell has a plurality of different resistances corresponding to respective ones of the different states; and
as a result of the accessing, applying a plurality of different signals to the memory cell to provide the memory cell with the different resistances including one of the resistances which corresponds to the desired state.

16. The method of claim 15 wherein the applying the different signals comprises applying to implement a single write operation with respect to the memory cell to program the memory cell to the desired state.

17. The method of claim 15 wherein the applying comprises first applying a first signal to attempt to provide the memory cell with the one resistance, second applying a second signal to provide the memory cell with a resistance which is different than the one resistance, and third applying a third signal to provide the memory cell with the one resistance.

18. The method of claim 15 wherein the applying the different signals comprises applying the different signals having different voltage polarities.

19. The method of claim 15 wherein the applying comprises applying one of the signals to provide the memory cell with another resistance which corresponds to a state which is different than the desired state.

20. The method of claim 15 wherein the memory cell has the one resistance corresponding to the desired state after the applying.

21. A memory system comprising:
a memory array comprising a plurality of memory cells; and
circuitry configured to:
access an instruction which instructs programming one of the memory cells to a desired one of a plurality of different states; and
as a result of the accessing the instruction, apply a plurality of signals to the one memory cell at different moments in time to provide the one memory cell in the desired state.

22. The system of claim 21 wherein the circuitry is configured to apply a plurality of the signals having a common polarity and to apply an additional signal having a polarity opposite to the common polarity intermediate the application of the signals having the common polarity.

23. The system of claim 21 wherein the circuitry is configured to apply the signals to implement a single write operation with respect to the one memory cell to program the one memory cell to the desired state.

24. The system of claim 21 wherein the circuitry is configured to apply one of the signals to provide the memory cell with a resistance which corresponds to a state which is different than the desired state.

25. The system of claim 21 wherein the memory cells individually comprise a plurality of terminals and a memory element intermediate the terminals which has different resistances corresponding to the different states.

26. The system of claim 25 wherein the one memory cell has an associated resistance corresponding to the desired state, and the circuitry is configured to apply a first of the signals to attempt to provide the memory cell with the associated resistance, to second apply a second of the signals to provide the memory cell with a resistance which is different than the associated resistance, and to third apply a third of the signals to provide the memory cell with the associated resistance.

Assignees

• Micron Technology Inc

Inventors

• Strand Jonathan
• Johnson Adam
• Chen Xiaonan
• Ramaswamy Durai Vishak Nirmal

Classifications

• G11C2013/0073

  Write using bi-directional cell biasing · CPC title

• G11C13/0064

  Verifying circuits or methods · CPC title

• G11C29/08

  Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C29/50008

  of impedance · CPC title