Partition and isolation of a processing-in-memory (PIM) device

Patent metadata

Field	Value
Publication number	US-11934827-B2
Application number	US-202117556291-A
Country	US
Kind code	B2
Filing date	Dec 20, 2021
Priority date	Dec 20, 2021
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

An apparatus that manages multi-process execution in a processing-in-memory (“PIM”) device includes a gatekeeper configured to: receive an identification of one or more registered PIM processes; receive, from a process, a memory request that includes a PIM command; if the requesting process is a registered PIM process and another registered PIM process is active on the PIM device, perform a context switch of PIM state between the registered PIM processes; and issue the PIM command of the requesting process to the PIM device.

First claim

What is claimed is:

1. An apparatus configured for managing multi-process execution in a processing-in-memory (PIM) device, the apparatus comprising a memory controller, the memory controller comprising logic configured to:
receive, from a first process, a memory request that includes a PIM command;
perform a context switch of a PIM state based on the first process being a registered PIM process and a second process being a registered PIM process and being active on the PIM device; and
issue the PIM command of the first process to the PIM device.

2. The apparatus of claim 1 , wherein the memory controller further comprises logic configured to:
if the first process is a registered PIM process and the first process is active on the PIM device, issue the PIM command to the PIM device, without performing a context switch of the PIM state.

3. The apparatus of claim 1 , wherein the memory controller further comprises logic configured to:
drop the memory request if the first process is not a registered PIM process.

4. The apparatus of claim 1 , wherein the memory controller further comprises logic configured to:
queue the memory request prior to performing the context switch of the PIM state.

5. The apparatus of claim 4 , wherein the memory controller queues the memory request for a predefined period of time before performing the context switch.

6. The apparatus of claim 5 , wherein the memory controller further comprises logic to reorder and batch queued memory requests from a same process prior to performing the context switch.

7. The apparatus of claim 1 , wherein:
the memory request is encoded with an identification of the first process; and
the memory controller further comprises logic configured to determine, based on the identification of the first process, whether another registered PIM process is active on the PIM device.

8. The apparatus of claim 1 , wherein the memory controller is further configured to process non-PIM memory requests concurrently with memory requests that include a PIM command.

9. The apparatus of claim 1 , wherein the memory controller further comprises logic to:
receive, from a PIM Driver, identifiers of registered PIM processes; and
store the identifiers of the registered PIM processes.

10. A method of managing multi-process execution in a processing-in-memory (PIM) device, method comprising:
receiving, from a first process, a memory request that includes a PIM command;
performing a context switch of a PIM state based on the first process being a registered PIM process and a second process being a registered PIM process and being active on the PIM device; and
issuing the PIM command of the first process to the PIM device.

11. The method of claim 10 , further comprising:
if the first process is a registered PIM process and the first process is active on the PIM device, issuing the PIM command to the PIM device, without performing a context switch of the PIM state.

12. The method of claim 11 , further comprising:
dropping the memory request if the first process is not a registered PIM process.

13. The method of claim 11 , further comprising:
queuing the memory request prior to performing the context switch of the PIM state.

14. The method of claim 11 , wherein the memory request is queued for a predefined period of time before performing the context switch.

15. The method of claim 14 , wherein queued memory requests of a same process are reordered and batched prior to performing the context switch.

16. The method of claim 10 , wherein the memory request is encoded with an identification of the first process and the method further comprises determining, based on the identification of the first process encoded in the memory request, whether another registered PIM process is active on the PIM device.

17. A computer program product comprising a non-transitory computer readable medium, wherein the medium includes instructions that when executed by a processor core:
receive, from a first process, a memory request that includes a processing-in-memory (PIM) command;
perform a context switch of a PIM state based on the first process being a registered PIM process and a second process being a registered PIM process and being active on a PIM device; and
issue a PIM command of the first process to the PIM device.

18. The computer program product of claim 17 , wherein the instructions, when executed by the processor core:
drop the memory request if the first process is not a registered PIM process.

19. The computer program product of claim 17 , wherein the instructions, when executed by the processor core:
issue the PIM command to the PIM device without performing a context switch of the PIM state if the first process is a registered PIM process and the first process is active on the PIM device.

20. The computer program product of claim 17 , wherein the instructions, when executed by the processor core:
queue the memory request prior to performing the context switch of the PIM state.

Assignees

• Advanced Micro Devices Inc

Inventors

• Puthoor Sooraj
• Hassaan Muhammad Amber
• Aji Ashwin
• Chu Michael L
• Jayasena Nuwan

Classifications

• G06F9/3004 Primary

  to perform operations on memory · CPC title

• G06F7/575 Primary

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/3856

  Reordering of instructions, e.g. using queues or age tags · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title