Register files for i/o packet compression

Patent metadata

Field	Value
Publication number	US-2017048358-A1
Application number	US-201615138485-A
Country	US
Kind code	A1
Filing date	Apr 26, 2016
Priority date	Aug 13, 2015
Publication date	Feb 16, 2017
Grant date	—

Abstract

Systems, apparatuses, and methods for reducing inter-node bandwidth are contemplated. A computer system includes requesting nodes sending transactions to target nodes. A requesting node sends a packet that includes a register identifier (ID) in place of a data value in the packet. The register ID indicates a register in the target node storing the data value. The register ID uses fewer bits in the packet than the data value. The data value may be a memory address referencing a memory location in the target node. The received packet may also include an opcode indicating an operation to perform on the targeted data value.

First claim

What is claimed is:

1 . A method comprising:
sending from a requesting node to a target node a request to allocate a register for use in the target node, the request including an address of a memory location in the target node; receiving by the requesting node a response to the request from the target node; sending a packet that corresponds to one or more transactions from the requesting node to the target node; wherein the packet comprises:
an address of a memory location in the target node, if the response indicates a register has not been allocated for use; and
a register identification (ID) of an allocated register in the target node, if the response indicates a register has been allocated for use by the requesting node.

2 . The method as recited in claim 1 , further comprising the target node:
receiving the request to allocate a register; responsive to determining a register is available, storing the address in the register and sending the register ID to the requesting node; and responsive to determining a register is not available, sending a response to the requesting node that indicates a register has not been allocated for use by the requesting node.

3 . The method as recited in claim 2 , further comprising:
receiving the packet at the target node; utilizing the register ID to identify the address that corresponds to the transaction; and utilizing the address to access the memory location in order to service the transaction.

4 . The method as recited in claim 1 , wherein the register comprises one of a dedicated register or a dynamically allocated memory location.

5 . The method as recited in claim 1 , wherein the packet comprises an opcode that indicates how to update a value stored in the register.

6 . The method as recited in claim 1 , further comprising the target node maintaining a mapping of the register ID to the address and automatically incrementing the address responsive to receiving a transaction of the one or more transactions.

7 . A computing system comprising:
a requesting node; and a target node coupled to the requesting node; wherein the requesting node is configured to:
send to the target node a request to allocate a register for use in the target node, the request including an address of a memory location in the target node;
receive a response to the request from the target node;
send a packet that corresponds to one or more transactions from the requesting node to the target node;
wherein the packet comprises:
an address of a memory location in the target node, if the response indicates a register has not been allocated for use; and
a register identification (ID) of an allocated register in the target node, if the response indicates a register has been allocated for use by the requesting node.

8 . The computing system as recited in claim 7 , wherein the target node is configured to:
receive the request to allocate a register; responsive to determining a register is available, store the address in the register and send the register ID to the requesting node; and responsive to determining a register is not available, send a response to the requesting node that indicates a register has not been allocated for use by the requesting node.

9 . The computing system as recited in claim 8 , wherein the target node is further configured to:
receive the packet; utilize the register ID to identify the address that corresponds to the transaction; and utilize the address to access the memory location in order to service the transaction.

10 . The computing system as recited in claim 7 , wherein the register comprises one of a dedicated register or a dynamically allocated memory location.

11 . The computing system as recited in claim 7 , wherein the packet comprises an opcode that indicates how to update a value stored in the register.

12 . The computing system as recited in claim 7 , wherein the target node is further configured to maintain a mapping of the register ID to the address and automatically increment the address responsive to receiving a transaction from the requesting node.

13 . The computing system as recited in claim 11 , wherein the opcode indicates one of an addition operation, a subtraction operation and a substitution operation.

14 . The computing system as recited in claim 8 , wherein the target node is further configured to deallocate the register previously allocated for the requesting node based on one or more of a priority level and a least-recently-used (LRU) value for the memory address stored in the register.

15 . A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable by a processor to:
send to a target node a request to allocate a register for use by a requesting node, the request including an address of a memory location in the target node; receive a response to the request from the target node; send a packet that corresponds to one or more transactions from the requesting node to the target node; wherein the packet comprises:
an address, responsive to the response indicating a register has not been allocated for use by the requesting node; and
a register identification (ID) of an allocated register in the target node, if the response indicates a register has been allocated for use by the requesting node.

16 . The non-transitory computer readable storage medium as recited in claim 15 , wherein the program instructions are further executable by a processor to:
receive the request to allocate a register; responsive to determining a register is available, store the address in the register and send the register ID to the requesting node; and responsive to determining a register is not available, send to the requesting node a response that indicates a register has not been allocated for use by the requesting node.

17 . The non-transitory computer readable storage medium as recited in claim 16 , wherein the program instructions are further executable by a processor to:
receive the packet at the target node; utilize the register ID to identify the address that corresponds to the transaction; and utilize the address to access the memory location in order to service the transaction.

18 . The non-transitory computer readable storage medium as recited in claim 15 , wherein the register comprises one of a dedicated register or a dynamically allocated memory location.

19 . The non-transitory computer readable storage medium as recited in claim 15 , wherein the packet comprises an opcode that indicates how to update the memory location.

20 . The non-transitory computer readable storage medium as recited in claim 15 , wherein the program instructions are further executable by a processor to maintain a mapping of the register ID to the address and automatically increment the address responsive to receiving a transaction of the one or more transactions.

Assignees

• Advanced Micro Devices Inc

Inventors

• Roberts David A
• Cheng Kevin Y
• Hu Nathan

Classifications

• H04L69/04 Primary

  Protocols for data compression, e.g. ROHC · CPC title

• G06F13/00

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• H04L45/74

  Address processing for routing · CPC title

• G06F13/38 Primary

  Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title

• G06F9/00

  Arrangements for program control, e.g. control units (program control for peripheral devices G06F13/10) · CPC title