Counter-based multiplication using processing in memory

Patent metadata

Field	Value
Publication number	US-11934798-B2
Application number	US-202016836773-A
Country	US
Kind code	B2
Filing date	Mar 31, 2020
Priority date	Mar 31, 2020
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

The present disclosure is directed to systems and methods for a memory device such as, for example, a Processing-In-Memory Device that is configured to perform multiplication operations in memory using a popcount operation. A multiplication operation may include a summation of multipliers being multiplied with corresponding multiplicands. The inputs may be arranged in particular configurations within a memory array. Sense amplifiers may be used to perform the popcount by counting active bits along bit lines. One or more registers may accumulate results for performing the multiplication operations.

First claim

The invention claimed is:

1. A system comprising:
at least one memory device;
at least one memory array of a memory device;
a plurality of memory cells of the at least one memory array, the plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines, wherein at least one multiplicand is stored in the memory array and at least one multiplier is stored in the memory device;
the at least one memory device being configured to:
generate a sum of the at least one multiplicand based on a plurality of popcount operations performed on the at least one multiplicand, wherein each of the plurality of popcount operations is configured to determine a total number of high bits present in a single word line of the plurality of word lines; and
generate a multiplication result based on the sum and by sequencing through bits of the multiplier.

2. The system of claim 1 , wherein the sum is generated based on accumulation of a current sum value with the popcount result, in response to the first bit of multiplier having a first predefined value at a corresponding position.

3. The system of claim 2 , wherein the sum is generated based on sequencing through positions without accumulating, in response to the bits of the multiplier having a second predefined value at corresponding positions.

4. The system of claim 1 , wherein at least one multiplicand is stored along a corresponding bit line.

5. The system of claim 4 , wherein the plurality of popcount operations comprises counting the number of bits having the first predefined value for each bit position of the at least one multiplicand.

6. The system of claim 5 , wherein the bit positions of the at least one multiplicand are stored along the same word line.

7. The system of claim 4 , further comprising a plurality of sense amplifiers, wherein each sense amplifier is coupled to a corresponding bit line, wherein the plurality of sense amplifiers are used to perform the plurality of popcount operations.

8. A system comprising:
at least one memory device;
at least one memory array of a memory device;
a plurality of memory cells of the at least one memory array, the plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines, wherein at least one multiplicand is stored in the memory array and at least one multiplier corresponding to the at least one multiplicand is stored in at least one bit line of the plurality of bit lines in the memory array; and
the memory device is further configured to generate a dot product result of the at least one multiplicand and the at least one multiplier based on a plurality of popcount operations performed on the at least one multiplicand, wherein the plurality of popcount operations are selectively performed by sequencing through bits of the at least one multiplier stored in the at least one bit line of the plurality of bit lines.

9. The system of claim 8 , wherein a set of popcount operations generates a popcount result for each bit position of bits of the at least one multiplier.

10. The system of claim 9 , wherein each popcount result is generated by selectively applying the plurality of popcount operations on the at least one multiplicand, and each popcount operation comprises counting the number of bits with a first value for each bit position of the at least one multiplicand.

11. The system of claim 10 , wherein each popcount result is generated in response to a bit of the at least one multiplier having a first predefined value at a corresponding bit position, and bypassed in response to a bit of the at least one multiplier having a second predefined value at a corresponding bit position.

12. The system of claim 10 , wherein the at least one multiplier is stored along odd-numbered bit lines, wherein the at least one multiplicand is stored along even-numbered bit lines.

13. The system of claim 10 , wherein each pair of consecutive bit lines is coupled to a respective sense amplifier.

14. The system of claim 10 , wherein each dot product calculation among a plurality of dot product calculation is generated from a group of multipliers with corresponding multiplicands.

15. A method comprising:
storing a plurality of multiplicand and corresponding multipliers in a memory device, the memory device comprising a plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines;
generating a dot product result by summing multiplications of each multiplicand and corresponding multiplier, wherein the dot product result is generated by:
sequencing through positions of bits of the multipliers;
selectively applying a plurality of popcount operations on the multiplicands based on the bit value of a current bit position of a corresponding multiplier to generate a popcount result, wherein each one of the plurality of popcount operations is performed on bits of a single word line of the at least one memory array; and
selectively accumulating the at least one popcount result;

wherein the dot product result is generated upon completing the sequencing.

16. The method of claim 15 , wherein the dot product result is generated as value in a feature map used in a convolutional neural network.

17. The method of claim 15 , wherein the multipliers are stored in a first memory array and wherein the multiplicands are stored in a second memory array that is different from the first memory array.

18. The method of claim 15 , wherein the multipliers are stored along odd-numbered bit lines, wherein the multiplicands are stored along even-numbered bit lines.

19. The method of claim 15 , wherein each pair of consecutive bit lines are coupled to a respective sense amplifier.

20. The method of claim 19 , wherein the sense amplifiers are used to perform the plurality of popcount operations.

21. A method comprising:
storing at least one summand in a memory array of a memory device, the memory array comprising a plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines;
generating a fused multiply-accumulation result by multiplying a multiplier by the popcount result of the at least one summand and accumulating it to the sum;
generating a popcount result by applying a plurality of popcount operations on the at least one summand, wherein each one of the plurality of popcount operations is performed on only one bit of each of the at least one summand; and
selectively accumulating a current sum value with the popcount result by sequencing through at least one bit of the multiplier;
wherein the fused multiply-accumulation result is generated upon completing the sequencing through the at least one bit of the multiplier.

22. A system comprising:
at least one memory device;
at least one memory array of a memory device;
a plurality of memory cells of the at least one memory array, the plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines, wherein at least one multiplicand is stored in the memory array and at least one multiplier corresponding to the at least one multiplicand is stored in the memory array; and
the memory device is further configured to generate a dot product result of the at least one multiplicand and the at least one multiplier based on a plurality of popcount operations performed on the at least one multiplicand, wherein the plurality of popcount operations are selectively performed by sequencing through bits of the at least one multiplier, wh

Assignees

• Micron Technology Inc

Inventors

• Yudanov Dmitri

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F7/607

  number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters (for applications thereof, see the relevant places, e.g. G06F7/49, G06F7/5013, G06F7/509, H03M1/00, H03M7/20) · CPC title

• G06F7/525

  in serial-serial fashion, i.e. both operands being entered serially (G06F7/533 takes precedence) · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title