Vector population count determination in memory

Patent metadata

Field	Value
Publication number	US-10146537-B2
Application number	US-201615065483-A
Country	US
Kind code	B2
Filing date	Mar 9, 2016
Priority date	Mar 13, 2015
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

First claim

What is claimed is:

1. A method, comprising:
determining, using sensing circuitry, a vector population of a number of elements of a vector stored in a memory array by:
determining a number of elements that represent a most significant bit of each of the number of elements;
determining an elemental mask for the vector, wherein the elemental mask represents a most significant bit of each of the number of elements;
performing a number of comparison iterations, wherein performing the number of comparison iterations comprises:
determining a reduction vector for each of the number of comparison iterations by performing a first loop in which a shifted elemental mask is formed by shifting bits of the elemental mask to the right by one bit and an OR operation is performed with the shifted elemental mask and the elemental mask; and
determining a pattern mask for each of the number of comparison iterations.

2. The method of claim 1 , comprising determining a quantity of the number of comparison iterations to perform by calculating log 2 of a number of bits in each of the number of elements.

3. The method of claim 1 , wherein performing the number of comparison iterations includes comparing 2 n bits during each respective comparison iteration.

4. The method of claim 1 , wherein determining the reduction vector for each of the number of comparison iterations includes performing a second loop, wherein a result of the first loop is shifted to the right by an amount equal to 2*I, where I is a count of the iteration that is being performed, and an OR operation is performed with the shifted result of the first loop and the result of the first loop.

5. The method of claim 1 , wherein determining the pattern mask for each of the number of comparison iterations includes determining a first portion of the pattern mask by performing an AND operation with the reduction vector and a destination vector and shifting a result of the AND operation to the right by 2 I-1 , where I is a count of the iteration that is being performed.

6. The method of claim 5 , wherein determining the pattern mask for each of the number of comparison iterations includes determining a second portion of the pattern mask by performing an AND operation with an inverse of the reduction vector and the destination vector.

7. The method of claim 6 , wherein performing the number of comparison iterations includes performing a half add operation of the first portion and second portion of the pattern mask for each of the number of comparison iterations.

8. The method of claim 7 , wherein performing the number of comparison iterations includes performing a loop that includes shifting a carry of the half add operation to left one place, and checking for carry values using a BlockOR operation, and performing another half add operation with the shift carry values and a sum of the half add operation.

Assignees

• Micron Technology Inc

Inventors

• Tiwari Sanjay

Classifications

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C2207/002

  Isolation gates, i.e. gates coupling bit lines to the sense amplifier · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C2207/005

  Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title