Vector-matrix multiplication using non-volatile memory cells

Patent metadata

Field	Value
Publication number	US-10528643-B1
Application number	US-201816052420-A
Country	US
Kind code	B1
Filing date	Aug 1, 2018
Priority date	Aug 1, 2018
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

Technology is described herein for performing multiplication using non-volatile memory cells. A multiplicand may be stored a node that includes multiple non-volatile memory cells. Each memory cell in a node may be programmed to one of two physical states, with each non-volatile memory cell storing a different bit of the multiplicand. Multiplication may be performed by applying a multiply voltage to the node of memory cells and processing memory cell currents from the memory cells in the node. The memory cell current from each memory cell in the node is multiplied by a different power of two. The multiplied signals are summed to generate a “result signal,’ which represents a product of the multiplier and a multiplicand stored in the node. If desired, “binary memory cells” may be used to perform multiplication. Vector/vector and vector/matrix multiplication may also be performed.

First claim

What is claimed is:

1. An apparatus, comprising:
one or more nodes of non-volatile memory cells;
a multiply circuit configured to simultaneously apply a multiply voltage to each non-volatile memory cell in a selected node, wherein each memory cell in the selected node passes a memory cell current in response to the multiply voltage, wherein a magnitude of the memory cell current depends on a magnitude of the multiply voltage and which physical state the memory cell is in, wherein the magnitude of the multiply voltage represents a multiplier;
a binary weighted summation circuit configured to:
multiply a magnitude of the memory cell current from each memory cell in the selected node by a different power of two to produce a multiplied signal for each memory cell; and
sum the multiplied signals for the selected node to generate a summed signal that represents a product of the multiplier times a multiplicand stored in the selected node.

2. The apparatus of claim 1 , wherein:
the binary weighted summation circuit configured to simultaneously multiply the magnitude of the memory cell current from each memory cell in the selected node and sum the multiplied signals for the selected node.

3. The apparatus of claim 1 , further comprising:
a write circuit configured to store one of “r” bits of the multiplicand into each memory cell in the selected node.

4. The apparatus of claim 1 , wherein the binary weighted summation circuit comprises:
multiply current mirrors, wherein each multiply current mirror produces a multiplied replica of one of the memory cell currents in order to generate one of the multiplied signals; and
a summing current mirror configured to combine the multiplied replicas from each of the multiply current mirrors to produce the summed signal.

5. The apparatus of claim 1 , wherein the binary weighted summation circuit is configured to:
convert the magnitude of the memory cell current from each memory cell into a digital value, and multiply each digital value by one of the different powers of two to generate each multiplied signal; and
sum the multiplied digital values to generate the summed signal.

6. The apparatus of claim 1 , further comprising:
a first conductive line connected to each non-volatile memory cell in the selected node; and
a plurality of second conductive lines, each second conductive line connected to one memory cell in the selected node, the multiply circuit configured to apply the multiply voltage between the first conductive line and each second conductive line in order to simultaneously apply the multiply voltage to each non-volatile memory cell in the selected node, the memory cell current of each non-volatile memory cell in the selected node passes to the second conductive line associated with the memory cell.

7. The apparatus of claim 1 , wherein:
the one or more nodes comprise “n” nodes of non-volatile memory cells, the selected node being one of the “n” nodes;
the multiply circuit configured to simultaneously apply “n” different multiply voltages to the “n” nodes, each of the n” different multiply voltages having a magnitude that represents one element of a first vector having “n” elements; and
the binary weighted summation circuit is further configured to generate a result signal that represents a product of the first vector times a second vector stored in the “n” nodes of non-volatile memory cells.

8. The apparatus of claim 7 , wherein:
the one or more nodes comprise “m” sets of the “n” nodes of memory cells; and
the binary weighted summation circuit is further configured to generate a matrix multiplication result that represents a product of the first vector and a matrix stored in the “m” sets of the “n” nodes of non-volatile memory cells.

9. A non-volatile memory system, comprising:
“n” nodes, each comprising “r” non-volatile memory cells;
“r” bit lines, each bit line associated with one memory cell in each of the “n” nodes; and
one or more control circuits in communication with the “n” nodes of non-volatile memory cells and the “r” bit lines, the one or more control circuits configured to:
simultaneously apply “n” vector element voltages to the respective “n” nodes, each memory cell in a node receives the same vector element voltage, each non-volatile memory cell causes a current in its associated bit line in response to the vector element voltage applied to that memory cell, wherein a magnitude of each vector element voltage represents a magnitude of one of “n” elements of a first vector;
multiply the current in each bit line by a different power of two; and
sum the multiplied currents in the “r” bit lines to generate a vector multiplication result signal that represents multiplication of the first vector by a second vector stored in the “n” nodes of non-volatile memory cells.

10. The non-volatile memory system of claim 9 , wherein the one or more control circuits are further configured to:
store the second vector in the “n” nodes of non-volatile memory cells, wherein each of the “n” nodes stores one of “n” elements of the second vector.

11. The non-volatile memory system of claim 10 , wherein:
each of the “n” elements of the second vector comprises “r” bits; and
for each of the “n” nodes, each memory cell stores one of the “r” bits of a corresponding element of the second vector.

12. A method of performing vector/vector multiply, the method comprising:
programming a plurality of non-volatile memory cells to one of a first state and a second state, the plurality of non-volatile memory cells comprising “n” nodes that each are programmed with one element of a first vector, each of “n” first conductive lines connected to a first terminal of each memory cell in a node, each node having “r” memory cells each connected to one of “r” second conductive lines;
generating “n” first voltages, wherein a magnitude of each of the “n” first voltages is based on a magnitude of one of “n” elements of a second vector;
simultaneously applying the “n” first voltages to corresponding ones of the “n” first conductive lines while applying a second voltage to a second terminal of each memory cell;
multiplying, by a different power of two, a current in each of the “r” second conductive lines that results from simultaneously applying the n” first voltages to corresponding ones of the “n” first conductive lines while applying the second voltage to the second terminal of each memory cell; and
summing each of the multiplied currents to generate a result that represents a dot product of the first vector by the second vector.

13. The method of claim 12 , further comprising digitizing information that represents the first vector into “r” bits for each of “n” elements of the first vector, and wherein:
programming the plurality of non-volatile memory elements comprises, for each of the “n” nodes, programming one of the “r” bits of one of the elements of the first vector into each of the non-volatile memory cells in the node.

14. The method of claim 12 , wherein programming the plurality of non-volatile memory cells to one of the first state and the second state comprises:
programming the plurality of non-volatile memory cells to one of a high conductance state and a low conductance state.

15. The method of claim 12 , wherein the multiplying and the summing are performed simultaneously.

16. The method of claim 12 , wherein:
multiplying the current in each of the second conductive lines comprises converting each of the currents into a digital value, and multiplying each digital value by one of the different powers of two; and
summing each of

Assignees

• Sandisk Technologies Llc

Inventors

• Choi Won Ho
• LUEKER-BODEN Martin

Classifications

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• G06F2207/4824

  Neural networks · CPC title

• G06F2207/4802

  Special implementations · CPC title