Etching platinum-containing thin film using protective cap layer

Patent metadata

Field	Value
Publication number	US-11929423-B2
Application number	US-202117347715-A
Country	US
Kind code	B2
Filing date	Jun 15, 2021
Priority date	Jan 19, 2017
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.

First claim

What is claimed is:

1. A microelectronic device, comprising:
a substrate; and
a platinum-containing layer over the substrate, the platinum-containing layer including a first segment and a second segment adjacent to the first segment, the platinum-containing layer having a first surface and a second surface opposite the first surface, where the second surface is closer to the substrate than the first surface;
wherein:
a first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface;
a width of the first segment along the first surface is less than twice a thickness of the first segment;
the second spacing is less than twice the thickness of the first segment;
a first platinum oxide layer is on the first segment of the platinum-containing layer at the first surface; and
a second platinum oxide layer is on the second segment of the platinum-containing layer at the first surface.

2. The microelectronic device of claim 1 , wherein the microelectronic device is free of platinum-containing residue on a top surface of the substrate between the first segment and the second segment.

3. The microelectronic device of claim 1 , further comprising a resistor formed in the platinum-containing layer.

4. The microelectronic device of claim 1 , further comprising an interconnect formed in the platinum-containing layer.

5. The microelectronic device of claim 4 , wherein the interconnect is a local interconnect.

6. The microelectronic device of claim 5 , wherein the interconnect makes an electrical connection to platinum silicide.

7. The microelectronic device of claim 1 , further comprising a bond pad formed in the platinum-containing layer.

8. The microelectronic device of claim 1 , further comprising a sensor element formed in the platinum-containing layer.

9. The microelectronic device of claim 1 , further comprising a thermocouple element formed in the platinum-containing layer.

10. The microelectronic device of claim 1 , further comprising a heater element formed in the platinum-containing layer.

11. The microelectronic device of claim 1 , wherein the first and second platinum oxide layers are formed based on an electrochemical process using an oxidizing electrolyte.

12. The microelectronic device of claim 1 , wherein:
a first edge of the first platinum oxide layer aligns with a corresponding edge of the first segment of the platinum-containing layer; and
a second edge of the second platinum oxide layer aligns with a corresponding edge of the second segment of the platinum-containing layer.

13. An integrated circuit, comprising:
a substrate; and
a plurality of platinum-containing conductive segments in a platinum-containing layer over the substrate, the plurality of platinum-containing conductive segments including first and second adjacent segments, the platinum-containing conductive segments having coplanar top surfaces and coplanar bottom surfaces, the bottom surfaces being closer to the substrate than are the top surfaces, and the bottom surfaces being wider than the top surfaces,
wherein:
the first and second conductive segments have a trapezoidal sectional profile such that a first spacing between the first conductive segment and the second conductive segment at the top surfaces is greater than a second spacing between the first conductive segment and the second conductive segment at the bottom surfaces;
a width of the first conductive segment along the top surface is less than twice a thickness of the first conductive segment;
the second spacing is less than twice the thickness of the first conductive segment;
a first platinum oxide layer is on the first conductive segment; and
a second platinum oxide layer is on the second conductive segment.

14. The integrated circuit of claim 13 , wherein a top surface of the substrate between the first segment and the second segment is free of platinum-containing residue.

15. The integrated circuit of claim 13 , further comprising a resistor formed in the platinum-containing layer.

16. The integrated circuit of claim 13 , further comprising an interconnect formed in the platinum-containing layer.

17. The integrated circuit of claim 16 , wherein the interconnect is a local interconnect.

18. The integrated circuit of claim 17 , wherein the interconnect makes a direct electrical connection to platinum silicide.

19. The integrated circuit of claim 13 , further comprising a bond pad formed in the platinum-containing layer.

20. The integrated circuit of claim 13 , further comprising a sensor element formed in the platinum-containing layer.

21. The integrated circuit of claim 13 , further comprising a thermocouple element formed in the platinum-containing layer.

22. The integrated circuit of claim 13 , further comprising a heater element formed in the platinum-containing layer.

23. The integrated circuit of claim 13 , wherein the first and second platinum oxide layers are formed based on an electrochemical process using an oxidizing electrolyte.

24. The integrated circuit of claim 13 , wherein:
a first edge of the first platinum oxide layer aligns with a corresponding edge of the first conductive segment; and
a second edge of the second platinum oxide layer aligns with a corresponding edge of the second conductive segment.

Assignees

• Texas Instruments Inc

Inventors

• Meier Sebastian
• Rinck Helmut
• Mittelstaedt Mike

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10P50/667

  by liquid etching only · CPC title

• H10P50/285

  of materials not containing Si, e.g. PZT or Al2O3 · CPC title