Semiconductor device including trench structure and manufacturing method

Patent metadata

Field	Value
Publication number	US-11929397-B2
Application number	US-202217583324-A
Country	US
Kind code	B2
Filing date	Jan 25, 2022
Priority date	Mar 7, 2019
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A semiconductor device includes: a silicon carbide semiconductor body having a source region of a first conductivity type and a body region of a second conductivity type; and a trench structure extending from a first surface into the silicon carbide semiconductor body along a vertical direction, the trench structure having a gate electrode and a gate dielectric. The trench structure is stripe-shaped and runs along a longitudinal direction that is perpendicular to the vertical direction. The source region includes a first source sub-region and a second source sub-region alternately arranged along the longitudinal direction. A doping concentration profile of the first source sub-region along the vertical direction differs from a doping concentration profile of the second source sub-region along the vertical direction. A corresponding method of manufacturing the semiconductor device is also described.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a silicon carbide semiconductor body comprising a source region of a first conductivity type and a body region of a second conductivity type;
a trench structure extending from a first surface into the silicon carbide semiconductor body along a vertical direction, the trench structure comprising a gate electrode and a gate dielectric,
wherein the trench structure is stripe-shaped and runs along a longitudinal direction that is perpendicular to the vertical direction,
wherein the source region comprises a first source sub-region and a second source sub-region alternately arranged along the longitudinal direction,
wherein a doping concentration profile of the first source sub-region along the vertical direction differs from a doping concentration profile of the second source sub-region along the vertical direction.

2. The semiconductor device of claim 1 , wherein an amount of doping of the first conductivity type is greater in the first source sub-region than in the second source sub-region.

3. The semiconductor device of claim 1 , further comprising a contact and a dielectric, wherein the contact is electrically connected to the source region at the first surface, wherein the contact directly adjoins at least a part of the first source sub-region at the first surface, and wherein the dielectric adjoins at least a part of the second source sub-region at the first surface.

4. The semiconductor device of claim 3 , wherein the contact comprises a positive temperature coefficient material directly adjoining the source region.

5. The semiconductor device of claim 1 , further comprising a doped region of the second conductivity type arranged between the second source sub-region and the first surface.

6. The semiconductor device of claim 1 , further comprising:
a current spread region of the first conductivity type; and
a drift region of the first conductivity type,
wherein the drift region is arranged between the current spread region and a semiconductor substrate of the first conductivity type and/or between the current spread region and a contact region of the first conductivity type, and/or between the current spread region and a buffer or drain region,
wherein a doping concentration of the current spread region is larger than a doping concentration of the drift region.

7. The semiconductor device of claim 1 , further comprising a shielding region of the second conductivity type directly adjoining at least a bottom part of the trench structure.

8. The semiconductor device of claim 1 , wherein the doping concentration profile of the first or the second source sub-region is larger than the doping concentration of the other one of the first or the second source sub-region in a region close to the first surface.

9. The semiconductor device of claim 1 , wherein the doping concentration profile of the first and the second source sub-regions converge at a depth below the first surface.

10. The semiconductor device of claim 1 , further comprising lattice defects in the second source sub-region, wherein the lattice defects reduce mobility of free charge carriers in the second source sub-region.

11. The semiconductor device of claim 1 , further comprising lattice defects in the second source sub-region, wherein the lattice defects reduce an effective n-type doping level in the second source sub-region.

12. A method of manufacturing a semiconductor device, the method comprising:
forming a source region of a first conductivity type and a body region of a second conductivity type in a silicon carbide semiconductor body; and
forming a trench structure extending from a first surface into the silicon carbide semiconductor body along a vertical direction, the trench structure comprising a gate electrode and a gate dielectric,
wherein the trench structure is stripe-shaped and runs along a longitudinal direction that is perpendicular to the vertical direction,
wherein the source region comprises a first source sub-region and a second source sub-region alternately arranged along the longitudinal direction,
wherein a doping concentration profile of the first source sub-region along a vertical direction differs from a doping concentration profile of the second source sub-region along the vertical direction.

13. The method of claim 12 , wherein forming the source region comprises two or more ion implantation processes having different ion implantation energies and/or ion implantation doses.

14. The method of claim 13 , wherein the two or more ion implantation processes are carried out based on different ion implantation masks.

15. The method of claim 13 , wherein the two or more ion implantation processes are carried out based on a common ion implantation mask.

16. The method of claim 12 , wherein forming the source region comprises introducing lattice defects in the second source sub-region by one or more ion implantation processes.

17. The method of claim 16 , wherein the lattice defects reduce mobility of free charge carriers in the second source sub-region.

18. The method of claim 16 , wherein the lattice defects reduce an effective n-type doping level in the second source sub-region.

19. The method of claim 12 , further comprising:
forming a doped region of the second conductivity type arranged between the second source sub-region and the first surface.

20. The method of claim 12 , further comprising:
forming a current spread region of the first conductivity type; and
forming a drift region of the first conductivity type,
wherein the drift region is arranged between the current spread region and a semiconductor substrate of the first conductivity type and/or between the current spread region and a contact region of the first conductivity type, and/or between the current spread region and a buffer or drain region,
wherein a doping concentration of the current spread region is larger than a doping concentration of the drift region.

Assignees

• Infineon Technologies Ag

Inventors

• Basler Thomas
• Leendertz Caspar
• Schulze Hans-Joachim

Classifications

• H10P30/22

  using masks · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/01

  Manufacture or treatment · CPC title