Semiconductor device

Patent metadata

Field	Value
Publication number	US-9825126-B2
Application number	US-201515502094-A
Country	US
Kind code	B2
Filing date	Sep 7, 2015
Priority date	Oct 20, 2014
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A source region of a MOSFET includes a source contact region connected to a source electrode, a source extension region adjacent to a channel region of a well region, and a source resistance control region provided between the source extension region and the source contact region. The source resistance control region includes a low concentration source resistance control region which has an impurity concentration lower than that of the source contact region or the source extension region and a high concentration source resistance control region which is formed between the well region and the low concentration source resistance control region and has an impurity concentration higher than that of the low concentration source resistance control region.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a first conductivity type drift layer formed on said semiconductor substrate;
a second conductivity type well region selectively formed on a surface layer part of said drift layer;
a first conductivity type source region formed on a surface layer part in said well region;
a JFET region which is a part of said drift layer adjacent to said well region;
a channel region which is a part of said well region sandwiched between said source region and said JFET region;
a gate electrode provided on said drift layer with a gate insulating film therebetween to extend across said source region, said channel region, and said JFET region;
a source electrode connected to said source region; and
a drain electrode formed on a back surface of said semiconductor substrate, wherein
said source region includes:
a source contact region formed on said surface layer part in said well region and connected to said source electrode;
a source extension region formed on said surface layer part in said well region and adjacent to said channel region; and
a source resistance control region provided between said source extension region and said source contact region, and
said source resistance control region includes:
a low concentration source resistance control region whose first conductivity type impurity concentration is lower than that of said source extension region or said source contact region; and
a high concentration source resistance control region which is formed between said well region and said low concentration source resistance control region and whose first conductivity type impurity concentration is higher than that of said low concentration source resistance control region.

2. A semiconductor device, comprising:
a semiconductor substrate;
a first conductivity type drift layer formed on said semiconductor substrate;
a second conductivity type well region selectively formed on a surface layer part of said drift layer;
a trench formed to pass through said well region to reach said drift layer;
a first conductivity type source region formed on a surface layer part in said well region to reach a sidewall of said trench;
a channel region which is a part of said well region sandwiched between said source region and said drift layer located below said well region and also adjacent to said trench;
a gate electrode provided in said trench with a gate insulating film therebetween to extend across said source region, said channel region, and said drift layer located below said well region;
a source electrode connected to said source region; and
a drain electrode formed on a back surface of said semiconductor substrate, wherein
said source region includes:
a source contact region formed on said surface layer part in said well region and connected to said source electrode;
a source extension region adjacent to said channel region; and
a source resistance control region provided between said source extension region and said source contact region, and
said source resistance control region includes:
a low concentration source resistance control region whose first conductivity type impurity concentration is lower than that of said source extension region or said source contact region; and
a high concentration source resistance control region which is formed between said well region and said low concentration source resistance control region and whose first conductivity type impurity concentration is higher than that of said low concentration source resistance control region.

3. The semiconductor device according to claim 1 , wherein
said high concentration source resistance control region is formed by performing an ion implantation on said surface layer part of said drift layer, and
a thickness of said high concentration source resistance control region is 0.1 μm to 3.0 μm.

4. The semiconductor device according to claim 1 , wherein
said high concentration source resistance control region is made up of an epitaxial growth layer formed on a surface of said drift layer, and
a thickness of said high concentration source resistance control region is 0.05 μm to 0.5 μm.

5. The semiconductor device according to claim 1 , wherein
a first conductivity type impurity concentration of said high concentration source resistance control region is larger by at least one digit than a first conductivity type impurity concentration of said low concentration source resistance control region.

6. The semiconductor device according to claim 1 , wherein
said high concentration source resistance control region is completely depleted by a depletion layer formed by a p-n junction between said source resistance control region and said well region in an on-state in a normal operation.

7. The semiconductor device according to claim 1 , wherein
said high concentration source resistance control region is not completely depleted by a depletion layer formed by a p-n junction between said source resistance control region and said well region in an on-state in a normal operation.

8. The semiconductor device according to claim 1 , wherein
a conductivity type of said low concentration source resistance control region is a second conductivity type.

9. The semiconductor device according to claim 1 , wherein
said well region has a retro-grade type impurity concentration profile.

10. The semiconductor device according to claim 1 , wherein
at least said low concentration source resistance control region, in said low concentration source resistance control region and said high concentration source resistance control region, is made up of an epitaxial growth layer formed on a surface of said drift layer.

11. The semiconductor device according to claim 10 , wherein
said epitaxial growth layer constituting said low concentration source resistance control region extends to a part located above said channel region and said drift layer adjacent to said channel region.

12. The semiconductor device according to claim 1 , further comprising
a Schottky electrode which is formed on said drift layer, Schottky-connected to said drift layer, and electrically connected to said source region.

13. The semiconductor device according to claim 2 , wherein
said high concentration source resistance control region is formed by performing an ion implantation on said surface layer part of said drift layer, and
a thickness of said high concentration source resistance control region is 0.1 μm to 3.0 μm.

14. The semiconductor device according to claim 2 , wherein
said high concentration source resistance control region is made up of an epitaxial growth layer formed on a surface of said drift layer, and
a thickness of said high concentration source resistance control region is 0.05 μm to 0.5 μm.

15. The semiconductor device according to claim 2 , wherein
a first conductivity type impurity concentration of said high concentration source resistance control region is larger by at least one digit than a first conductivity type impurity concentration of said low concentration source resistance control region.

16. The semiconductor device according to claim 2 , wherein
said high concentration source resistance control region is completely depleted by a depletion layer formed by a p-n junction between said source resistance control region and said well region in an on-state in a normal operation.

17. The semiconductor device according to claim 2 , wherein
said high concentration source resistance control region

Assignees

• Mitsubishi Electric Corp

Inventors

• Hatta Hideyuki
• Miura Naruhisa

Classifications

• H10P30/22

  using masks · CPC title

• H01L27/075

  Electricity · mapped topic

• H01L29/7813

  Electricity · mapped topic

• H01L29/063 Primary

  Electricity · mapped topic

• H01L29/7806

  Electricity · mapped topic