Lithographic cavity formation to enable EMIB bump pitch scaling

US11929330B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11929330-B2
Application numberUS-202217712944-A
CountryUS
Kind codeB2
Filing dateApr 4, 2022
Priority dateMar 23, 2018
Publication dateMar 12, 2024
Grant dateMar 12, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic package, comprising: a first layer, wherein the first layer comprises an organic material; a second layer over the first layer, wherein the second layer comprises an organic material; a conductive pillar in the second layer; a cavity through the second layer to expose a first surface of the first layer; a bridge substrate in the cavity, wherein the bridge substrate is supported by and in contact with the first surface of the first layer; and a third layer, wherein the third layer fills the cavity and is over a top surface of the second layer, wherein the third layer has a planar surface over an entirety of the bridge substrate, and wherein the third layer is a single layer having a same composition continuous throughout the third layer. 2. The electronic package of claim 1 , wherein the cavity includes a first portion and a second portion above the first portion, wherein a width of the first portion is greater than a width of the second portion. 3. The electronic package of claim 2 , wherein a height of the first portion of the cavity is equal to a height of a first conductive layer over the first layer. 4. The electronic package of claim 3 , wherein a height of the second portion of the cavity is equal to a height of the conductive pillar over the first conductive layer. 5. The electronic package of claim 2 , wherein a sidewall surface of the first portion of the cavity and a sidewall surface of the second portion of the cavity are substantially vertical. 6. The electronic package of claim 1 , wherein the third layer conforms to sidewall surfaces of the cavity. 7. The electronic package of claim 1 , further comprising: a conductive layer over the third layer, wherein the conductive layer is electrically coupled to a contact pad on the bridge substrate with a via through a portion of the third layer. 8. The electronic package of claim 1 , wherein a top surface of the second layer is above a top surface of the bridge substrate. 9. An electronic package, comprising: a first layer, wherein the first layer comprises an organic material; a second layer over the first layer, wherein the second layer comprises an organic material; a conductive pillar in the second layer; a cavity through the second layer to expose a first surface of the first layer, wherein the cavity includes a first portion and a second portion above the first portion, wherein a width of the first portion is greater than a width of the second portion; and a bridge substrate in the cavity, wherein the bridge substrate is supported by and in contact with the first surface of the first layer. 10. The electronic package of claim 9 , wherein a height of the first portion of the cavity is equal to a height of a first conductive layer over the first layer. 11. The electronic package of claim 10 , wherein a height of the second portion of the cavity is equal to a height of the conductive pillar over the first conductive layer. 12. The electronic package of claim 9 , wherein a sidewall surface of the first portion of the cavity and a sidewall surface of the second portion of the cavity are substantially vertical. 13. The electronic package of claim 9 , wherein a top surface of the second layer is above a top surface of the bridge substrate. 14. An electronic package, comprising: a first layer, wherein the first layer comprises an organic material; a second layer over the first layer, wherein the second layer comprises an organic material; a conductive pillar in the second layer; a cavity through the second layer to expose a first surface of the first layer; a bridge substrate in the cavity, wherein the bridge substrate is supported by and in contact with the first surface of the first layer; a third layer, wherein the third layer fills the cavity and is over a top surface of the second layer, and wherein the third layer is a single layer having a same composition continuous throughout the third layer; and a conductive layer over the third layer, wherein the conductive layer is electrically coupled to a contact pad on the bridge substrate with a via through a portion of the third layer. 15. The electronic package of claim 14 , wherein the third layer conforms to sidewall surfaces of the cavity. 16. The electronic package of claim 14 , wherein a top surface of the second layer is above a top surface of the bridge substrate. 17. An electronic package, comprising: a first layer, wherein the first layer comprises an organic material; a second layer over the first layer, wherein the second layer comprises an organic material; a conductive pillar in the second layer; a cavity through the second layer to expose a first surface of the first layer, wherein the cavity includes a first portion and a second portion above the first portion, wherein a width of the first portion is greater than a width of the second portion; a bridge substrate in the cavity, wherein the bridge substrate is supported by and in contact with the first surface of the first layer; and a third layer, wherein the third layer fills the cavity and is over a top surface of the second layer, and wherein the third layer has a planar surface over an entirety of the bridge substrate. 18. The electronic package of claim 17 , wherein a height of the first portion of the cavity is equal to a height of a first conductive layer over the first layer. 19. The electronic package of claim 18 , wherein a height of the second portion of the cavity is equal to a height of the conductive pillar over the first conductive layer. 20. The electronic package of claim 17 , wherein a sidewall surface of the first portion of the cavity and a sidewall surface of the second portion of the cavity are substantially vertical.

Assignees

Inventors

Classifications

  • Dispositions, e.g. layouts · CPC title

  • characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

  • Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

  • Shapes or dispositions of interconnections · CPC title

  • Vias, e.g. via plugs · CPC title

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Frequently asked questions

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What does patent US11929330B2 cover?
Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supp…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W70/611. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 12 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).