Light-emitting diode packages with individually controllable light-emitting diode chips
US-2019363232-A1 · Nov 28, 2019 · US
US11929305B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11929305-B2 |
| Application number | US-202117532446-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 22, 2021 |
| Priority date | Nov 23, 2020 |
| Publication date | Mar 12, 2024 |
| Grant date | Mar 12, 2024 |
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In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.
Opening claim text (preview).
What is claimed is: 1. A method, comprising: forming a first electrostatic discharge protection device structure in a first area on a front side of a semiconductor substrate; forming a first contact pad on the first electrostatic discharge protection device structure and a second contact pad in a second area on the front side of the semiconductor substrate; thinning the semiconductor substrate from a back side of the semiconductor substrate; forming a metal connection connecting the first electrostatic discharge protection device structure to the second area; and providing a carrier material to the back side of the semiconductor substrate after forming the metal connection. 2. The method of claim 1 , wherein providing the carrier material comprises molding the carrier material on the back side of the semiconductor substrate. 3. The method of claim 1 , wherein the metal connection covers only part of an area of the first electrostatic discharge protection device structure in a cross-sectional view. 4. The method of claim 1 , wherein the first electrostatic discharge protection device structure comprises a Zener diode structure. 5. The method of claim 1 , wherein the metal connection is electrically coupled to the second contact pad. 6. The method of claim 1 , further comprising forming a second electrostatic discharge protection device structure between the metal connection and the second contact pad. 7. The method of claim 1 , wherein forming the first electrostatic discharge protection device structure comprises forming one or more highly doped layers by diffusion doping or by implantation. 8. The method of claim 1 , further comprising: forming a third electrostatic discharge protection device structure in the second area; and forming a further metal connection between the third electrostatic discharge protection device structure and the first area. 9. The method of claim 8 , wherein the third electrostatic discharge protection device structure is a same type of device structure as the first electrostatic discharge protection device structure. 10. The method of claim 9 , further comprising forming a fourth electrostatic discharge protection device structure between the further metal connection and the fourth contact pad. 11. The method of claim 1 , further comprising, during front side processing, removing semiconductor material between the first area and the second area.
Manufacture or treatment · CPC title
Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title
using diodes as protective elements · CPC title
characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title
using silicon technology, e.g. SiGe · CPC title
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