Sense amplifier, memory and method for controlling sense amplifier

Patent metadata

Field	Value
Publication number	US-11929111-B2
Application number	US-202117472157-A
Country	US
Kind code	B2
Filing date	Sep 10, 2021
Priority date	Sep 1, 2020
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module, arranged to read data in a memory cell; and a control module, electrically connected to the amplification module. In a first offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first inverter and a second inverter, and each of the first inverter and the second inverter is an inverter an input terminal and an output terminal connected to each other; and in a second offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a current mirror structure.

First claim

The invention claimed is:

1. A sense amplifier, comprising:
an amplification circuit, arranged to read data in a memory cell and comprising a plurality of transistors; and
a control circuit, electrically connected to the amplification circuit and comprising a plurality of switches,
wherein in a first offset compensation stage of the sense amplifier, the control circuit is arranged to control, through controlling on-off states of the plurality of switches by receiving at least one control signal, the plurality of transistors of the amplification circuit to form a first inverter and a second inverter, each of the first inverter and the second inverter being an inverter with an input terminal and an output terminal connected to each other; and
in a second offset compensation stage of the sense amplifier, the control circuit is arranged to control, through controlling the on-off states of the plurality of switches by receiving the at least one control signal, a first part of the plurality of transistors of the amplification circuit to form a current mirror structure,
wherein the plurality of transistors of the amplification circuit comprise:
a first P-channel Metal Oxide Semiconductor (PMOS) transistor;
a second PMOS transistor;
a first N-channel Metal Oxide Semiconductor (NMOS) transistor, a gate of the first NMOS transistor being connected to a first bitline, and a drain of the first NMOS transistor being connected to a drain of the first PMOS transistor through a first node; and
a second NMOS transistor, a gate of the second NMOS transistor being connected to a second bitline, and a drain of the second NMOS transistor being connected to a drain of the second PMOS transistor through a second node,

wherein in the first offset compensation stage of the sense amplifier, the first PMOS transistor and the first NMOS transistor are configured as the first inverter, and the second PMOS transistor and the second NMOS transistor are configured as the second inverter.

2. The sense amplifier of claim 1 , wherein the plurality of switches of the control circuit comprise:
a first switch, a first terminal of the first switch being connected to the first node, and a second terminal of the first switch being connected to a gate of the first PMOS transistor;
a second switch, a first terminal of the second switch being connected to the gate of the first PMOS transistor, and a second terminal of the second switch being connected to the second node;
a third switch, a first terminal of the third switch being connected to a gate of the second PMOS transistor, and a second terminal of the third switch being connected to the first node;
a fourth switch, a first terminal of the fourth switch being connected to the second node, and a second terminal of the fourth switch being connected to the gate of the second PMOS transistor;
a fifth switch, a first terminal of the fifth switch being connected to the first bitline, and a second terminal of the fifth switch being connected to the first node; and
a sixth switch, a first terminal of the sixth switch being connected to the second bitline, and a second terminal of the sixth switch being connected to the second node,
wherein in the first offset compensation stage of the sense amplifier, the first switch, the fourth switch, the fifth switch and the sixth switch are turned on, and the second switch and the third switch are turned off.

3. The sense amplifier of claim 2 , wherein in the first offset compensation stage of the sense amplifier, a source of each of the first PMOS transistor and the second PMOS transistor receives a first voltage, and a source of each of the first NMOS transistor and the second NMOS transistor is grounded.

4. The sense amplifier of claim 3 , wherein in a case of reading the data in the memory cell on the first bitline, in the second offset compensation stage of the sense amplifier, the first switch, the third switch and the sixth switch are turned on, and the second switch, the fourth switch and the fifth switch are turned off,
wherein in a case that the first switch and the third switch are turned on, the first PMOS transistor and the second PMOS transistor are configured as a first current mirror structure.

5. The sense amplifier of claim 3 , wherein in a case of reading the data in the memory cell on the second bitline, in the second offset compensation stage of the sense amplifier, the first switch, the third switch and the sixth switch are turned off, and the second switch, the fourth switch and the fifth switch are turned on,
wherein in a case that the second switch and the fourth switch are turned on, the first PMOS transistor and the second PMOS transistor are configured as a second current mirror structure.

6. The sense amplifier of claim 4 , wherein in the case of reading the data in the memory cell on the first bitline, in a first amplification stage of the sense amplifier, the control circuit is arranged to control, through controlling the on-off states of the plurality of switches by receiving the at least one control signal, a second part of the plurality of transistors of the amplification circuit to form a third inverter.

7. The sense amplifier of claim 6 , wherein in the case of reading the data in the memory cell on the first bitline, in the first amplification stage of the sense amplifier, the second PMOS transistor and the second NMOS transistor are controlled to be in a cut-off region, and the first PMOS transistor and the first NMOS transistor are configured to form the third inverter.

8. The sense amplifier of claim 5 , wherein in the case of reading the data in the memory cell on the second bitline, in a first amplification stage of the sense amplifier, the control circuit is arranged to control, through controlling the on-off states of the plurality of switches by receiving the at least one control signal, a second part of the plurality of transistors of the amplification circuit to form a fourth inverter.

9. The sense amplifier of claim 8 , wherein in the case of reading the data in the memory cell on the second bitline, in the first amplification stage of the sense amplifier, the first PMOS transistor and the first NMOS transistor are controlled to be in a cut-off region, and the second PMOS transistor and the second NMOS transistor are configured to form the fourth inverter.

10. The sense amplifier of claim 6 , wherein the plurality of switches of the control circuit further comprise:
a seventh switch, a first terminal of the seventh switch being connected to the first bitline, and a second terminal of the seventh switch being connected to the second node; and
an eighth switch, a first terminal of the eighth switch being connected to the second bitline, and a second terminal of the eighth switch being connected to the first node,
wherein in the first offset compensation stage and the second offset compensation stage of the sense amplifier, the seventh switch and the eighth switch are turned off; and
in the first amplification stage of the sense amplifier, the first switch, the fourth switch, the fifth switch and the sixth switch are turned off, and the second switch, the third switch, the seventh switch and the eighth switch are turned on.

11. The sense amplifier of claim 7 , wherein in the case of reading the data in the memory cell on the first bitline, in the first amplification stage of the sense amplifier, the source of the first PMOS transistor receives the first voltage, the source of the first NMOS transistor is grounded, and the source of the second PMOS transistor and the source of the second NMOS transistor receive a second voltage,
wherein the second voltage is less than the first voltage.

Assignees

• Univ Anhui
• Changxin Memory Tech Inc

Inventors

• Lin Zhiting
• Wen Guanglei
• He Jun
• Ying Zhan
• Li Xin
• Cao Kanyu
• Lu Wenjuan
• Peng Chunyu
• Wu Xiulong
• Chen Junning

Classifications

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title