Dynamic abstract generation and synthesis flow with area prediction

Patent metadata

Field	Value
Publication number	US-11928409-B2
Application number	US-202217567328-A
Country	US
Kind code	B2
Filing date	Jan 3, 2022
Priority date	Jan 3, 2022
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A computer-implemented method includes receiving, by a processor, a physical design block and a physical hierarchy of a chip design of a chip. Further, the method includes extracting, by the processor, one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design. Further, the method includes predicting, by the processor, specifications of the macro to be added to the chip design based on the physical design block, the predicting performed using a pre-trained machine learning model. Further, the method includes using, by the processor, the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.

First claim

What is claimed is:

1. A computer-implemented method comprising:
receiving, by a processor, a physical design block and a physical hierarchy of a chip design of a chip;
extracting, by the processor, one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design;
receiving, by the processor, additional constraints as parameters for the macro, the additional constraints including a highest level of metal that can be used by the macro, an optimization option for the macro, a desired aspect ratio of the macro, and an uplift factor of the macro;
predicting, by the processor, specifications of the macro to be added to the chip design based on the physical design block and the additional constraints, the predicting performed using a pre-trained machine learning model;
using, by the processor, the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.

2. The computer-implemented method of claim 1 , wherein the physical design block is provided in a hardware descriptive language.

3. The computer-implemented method of claim 1 , wherein, the one or more features of the macro extracted by the processor comprise a count of sequential elements, a count of combinational elements, a count of connectivity of each component, a count of primary input ports, a count of output ports.

4. The computer-implemented method of claim 1 , wherein the specifications of the macro predicted by the machine learning model comprise an area and an aspect ratio of the macro.

5. The computer-implemented method of claim 1 , wherein the machine learning model is a multi-output regression model.

6. The computer-implemented method of claim 1 , wherein extracting the one or more features of the macro further comprises mapping components of the macro with a bill of materials based on the physical design.

7. The computer-implemented method of claim 1 , wherein the pre-trained machine learning model is further provided one or more design guidelines that comprise constraints regarding placement of one or more components.

8. A system comprising:
a memory; and
one or more processing units coupled with the memory, the one or more processing units are configured to perform a method to support a design cycle of a chip, wherein performing the method comprises:
receiving a physical design block and a physical hierarchy of a chip design of the chip;
extracting one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design;
receiving, by the processor, additional constraints as parameters for the macro, the additional constraints including a highest level of metal that can be used by the macro, an optimization option for the macro, a desired aspect ratio of the macro, and an uplift factor of the macro;
predicting specifications of the macro to be added to the chip design based on the physical design block and the additional constraints, the predicting performed using a pre-trained machine learning model;
using the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.

9. The system of claim 8 , wherein the physical design block is provided in a hardware descriptive language.

10. The system of claim 8 , wherein, the one or more features of the macro extracted by the processor comprise a count of sequential elements, a count of combinational elements, a count of connectivity of each component, a count of primary input ports, a count of output ports.

11. The system of claim 8 , wherein the specifications of the macro predicted by the machine learning model comprise an area and an aspect ratio of the macro.

12. The system of claim 8 , wherein the machine learning model is a multi-output regression model.

13. The system of claim 8 , wherein extracting the one or more features of the macro further comprises mapping components of the macro with a bill of materials based on the physical design.

14. The system of claim 8 , wherein the pre-trained machine learning model is further provided one or more design guidelines that comprise constraints regarding placement of one or more components.

15. A computer program product comprising a computer-readable memory that has computer-executable instructions stored thereupon, the computer-executable instructions when executed by a processor cause the processor to perform a method that comprises:
receiving a physical design block and a physical hierarchy of a chip design of a chip;
extracting one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design;
receiving, by the processor, additional constraints as parameters for the macro, the additional constraints including a highest level of metal that can be used by the macro, an optimization option for the macro, a desired aspect ratio of the macro, and an uplift factor of the macro;
predicting specifications of the macro to be added to the chip design based on the physical design block and the additional constraints, the predicting performed using a pre-trained machine learning model;
using the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.

16. The computer program product of claim 15 , wherein the physical design block is provided in a hardware descriptive language.

17. The computer program product of claim 15 , wherein, the one or more features of the macro extracted by the processor comprise a count of sequential elements, a count of combinational elements, a count of connectivity of each component, a count of primary input ports, a count of output ports.

18. The computer program product of claim 15 , wherein the specifications of the macro predicted by the machine learning model comprise an area and an aspect ratio of the macro.

19. The computer program product of claim 15 , wherein the machine learning model is a multi-output regression model.

20. The computer program product of claim 15 , wherein extracting the one or more features of the macro further comprises mapping components of the macro with a bill of materials based on the physical design.

Assignees

• IBM

Inventors

• Lewis Daniel
• Rao Rahul M

Classifications

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/323

  Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/27

  using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title