Usage-based temporal degradation estimation for memory elements
US-9064071-B2 · Jun 23, 2015 · US
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Rao Rahul M patents
Rao Rahul M is listed as an inventor on 4 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Rao Rahul M |
| Total patents | 4 |
| First publication | Feb 24, 2015 |
| Latest publication | Jun 23, 2015 |
Notable patents
Publications ranked by popularity score, then publication date.
Usage-based temporal degradation estimation for memory elements
US-9058448-B2 · Jun 16, 2015 · US
Estimating delay deterioration due to device degradation in integrated circuits
US-2015154331-A1 · Jun 4, 2015 · US
Estimating delay deterioration due to device degradation in integrated circuits
US-8966420-B2 · Feb 24, 2015 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 4 |
| Bansal Aditya | 3 |
| Kim Jae-Joon | 3 |
| Rao Rahul M | 3 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G01R31/31725 | 2 |
| G01R31/3016 | 2 |
| G06F30/39 | 2 |
| G01R31/2881 | 2 |
| G06F2119/12 | 2 |