Generation of dynamic design flows for integrated circuits

Patent metadata

Field	Value
Publication number	US-11630930-B2
Application number	US-202117361253-A
Country	US
Kind code	B2
Filing date	Jun 28, 2021
Priority date	May 2, 2019
Publication date	Apr 18, 2023
Grant date	Apr 18, 2023

Abstract

Systems and methods are disclosed for to generation of dynamic design flows for integrated circuits. For example, a method may include accessing a design flow configuration data structure, wherein the design flow configuration data structure is encoded in a tool control language; based on the design flow configuration data structure, selecting multiple flowmodules from a set of flowmodules, wherein each flowmodule provides an application programming interface, in the tool control language, to a respective electronic design automation tool; based on the design flow configuration data structure, generating a design flow as a directed acyclic graph including the selected flowmodules as vertices; and generating an output integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the design flow to control the respective electronic design automation tools of the selected flowmodules.

First claim

What is claimed is:

1. A method comprising:
based on a design flow configuration data structure, selecting multiple flowmodules from a set of flowmodules, wherein each flowmodule in the set of flowmodules provides an application programming interface to a respective electronic design automation tool;
based on the design flow configuration data structure, generating a design flow as a directed acyclic graph including the selected flowmodules as vertices;
generating an output integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the design flow to control the respective electronic design automation tools of the selected flowmodules; and
transmitting, storing, or displaying the output integrated circuit design data structure.

2. The method of claim 1 , in which generating the design flow comprises:
generating, based on the design flow configuration data structure, a first design flow;

generating a current integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the first design flow;
determining one or more parameters of the current integrated circuit design data structure;
inputting the one or more parameters to a machine learning module to obtain one or more feedback parameters as output of the machine learning module; and
generating, based on the one or more feedback parameters, a next design flow.

3. The method of claim 2 , wherein the one or more parameters of the current integrated circuit design data structure include estimates of power, performance, and area for an integrated circuit described by the current integrated circuit design data structure.

4. The method of claim 1 , comprising:
generating a graphical representation of the directed acyclic graph of the design flow; and
transmitting, storing, or displaying the graphical representation.

5. The method of claim 1 , wherein the design flow includes a vertex corresponding to a task for hypertext markup language generation, comprising:
generating a hypertext markup language data structure, based on the output integrated circuit design data structure, using the design flow; and
transmitting, storing, or displaying the hypertext markup language data structure.

6. The method of claim 1 , wherein the design flow configuration data structure is part of a design parameters data structure, comprising:
accessing the design parameters data structure, wherein the design parameters data structure includes values of design parameters of an integrated circuit design;
responsive to a command identifying the design parameters data structure, generating a register-transfer level data structure for an integrated circuit based on the design parameters data structure;
responsive to the command identifying the design parameters data structure, generating a software development kit for the integrated circuit based on the register-transfer level data structure;
wherein the multiple flowmodules are selected responsive to the command identifying the design parameters data structure;
wherein the design flow is generated responsive to the command identifying the design parameters data structure;
wherein the output integrated circuit design data structure includes a physical design data structure for the integrated circuit that is generated, responsive to the command identifying the design parameters data structure, based on the register-transfer level data structure;
responsive to the command identifying the design parameters data structure, generating a test plan for the integrated circuit based on the design parameters data structure and acceptance criteria;
responsive to the command identifying the design parameters data structure, invoking tests for the integrated circuit based on the test plan, the register-transfer level data structure, the software development kit, and the physical design data structure to obtain a set of test results; and
transmitting, storing, or displaying a design data structure based on the register-transfer level data structure, the software development kit, the physical design data structure, and the test results.

7. The method of claim 6 , comprising:
transmitting a physical design specification based on the physical design data structure to a server to invoke manufacturing of the integrated circuit.

8. A system comprising:
a network interface;
a memory; and
a processor, wherein the memory includes instructions executable by the processor to cause the system to:
based on a design flow configuration data structure, select multiple flowmodules from a set of flowmodules, wherein each flowmodule in the set of flowmodules provides an application programming interface to a respective electronic design automation tool;
based on the design flow configuration data structure, generate a design flow as a directed acyclic graph including the selected flowmodules as vertices; and
generate an output integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the design flow to control the respective electronic design automation tools of the selected flowmodules.

9. The system of claim 8 , wherein the memory includes instructions executable by the processor to cause the system to:
generate, based on the design flow configuration data structure, a first design flow;
generate a current integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the first design flow;
determine one or more parameters of the current integrated circuit design data structure;
input the one or more parameters to a machine learning module to obtain one or more feedback parameters as output of the machine learning module; and
generate, based on the one or more feedback parameters, a next design flow.

10. The system of claim 9 , wherein the one or more parameters of the current integrated circuit design data structure include estimates of power, performance, and area for an integrated circuit described by the current integrated circuit design data structure.

11. The system of claim 8 , wherein the memory includes instructions executable by the processor to cause the system to:
generate a graphical representation of the directed acyclic graph of the design flow; and
transmit, store, or display the graphical representation.

12. The system of claim 8 , wherein the design flow configuration data structure is part of a design parameters data structure, and the memory includes instructions executable by the processor to cause the system to:
access the design parameters data structure, wherein the design parameters data structure includes values of design parameters of an integrated circuit design;
responsive to a command identifying the design parameters data structure, generate a register-transfer level data structure for an integrated circuit based on the design parameters data structure;
responsive to the command identifying the design parameters data structure, generate a software development kit for the integrated circuit based on the register-transfer level data structure;
wherein the multiple flowmodules are selected responsive to the command identifying the design parameters data structure;
wherein the design flow is generated responsive to the command identifying the design parameters data structure;
wherein the output integrated circuit design data structure includes a physical design data structure for the integrated circuit that is generated, responsive to the command identifying the design parameters data structure, based on the register-transfer

Assignees

• Sifive Inc

Inventors

• Chen Han

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/27

  using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title

• G06F30/331

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title