Deformable array of semiconductor devices

Patent metadata

Field	Value
Publication number	US-11923472-B2
Application number	US-201916668715-A
Country	US
Kind code	B2
Filing date	Oct 30, 2019
Priority date	Nov 5, 2018
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

A deformable array of semiconductor devices, and a method of manufacturing such a deformable array. The deformable array comprises a plurality of islands, where each island contains at least one semiconductor device, and the plurality of islands are arranged in an auxetic geometry.

First claim

The invention claimed is:

1. A deformable array of semiconductor devices comprising:
a plurality of triangular islands, where each triangular island comprises at least one semiconductor device and the plurality of triangular islands are arranged in an auxetic geometry so that the array exhibits a negative Poisson's ratio when loaded under tensile strain; and
a plurality of serpentine interconnects coupling the plurality of triangular islands to one another, each having a first end which connects to one triangular island and a second end which connects to an adjacent triangular island and a plurality of bends therebetween,
wherein the triangular islands and the serpentine interconnects lie in the same plane in an unstretched condition, and
wherein, in the unstretched condition, each serpentine interconnect couples, at its first end, to the one triangular island near one corner of the one triangular island, extends in a direction toward another corner of the one triangular island, bends in the same plane to extend in the opposite direction to back towards the one corner of the one triangular island, at least twice, and couples, at its second end, to the adjacent triangular island.

2. The deformable array of semiconductor devices of claim 1 wherein the serpentine interconnects also comprise PN junctions.

3. The deformable array of semiconductor devices of claim 2 wherein the serpentine interconnects comprise lateral (side-by-side) PN junctions.

4. The deformable array of semiconductor devices of claim 2 wherein the serpentine interconnects comprise vertical PN junctions.

5. The deformable array of semiconductor devices of claim 1 wherein each triangular island has a PN junction on a sidewall thereof.

6. The deformable array of semiconductor devices of claim 5 wherein the PN junctions on the sidewalls of the triangular islands form solar cells.

7. The deformable array of semiconductor devices of claim 6 wherein the PN junctions on the sidewalls of the triangular islands provide additional active solar cell area.

8. The deformable array of semiconductor devices of claim 1 wherein the auxetic geometry maintains functionality under a uniaxial strain of at least 20%.

9. The deformable array of semiconductor devices of claim 1 wherein the auxetic geometry maintains functionality under a biaxial strain of at least 20%.

10. The deformable array of semiconductor devices of claim 1 wherein the serpentine interconnects have curved or rectangular corners at the bends.

11. The deformable array of semiconductor devices of claim 1 , wherein six adjacent triangular islands and the serpentine interconnects coupling the six adjacent triangular islands together are arranged around a common point to form a hexagon-shape in an unstretched condition.

12. The deformable array of semiconductor devices of claim 1 , wherein the triangular islands and the serpentine interconnects substantially lie in the same plane in the unstretched and a stretched condition.

13. The deformable array of semiconductor devices of claim 1 , wherein the triangular islands and the serpentine interconnects have the same thickness.

14. The deformable array of semiconductor devices of claim 1 , wherein, in the unstretched position, each serpentine interconnect is positioned between the sidewalls of the one triangular island and the adjacent triangular island.

15. The deformable array of semiconductor devices of claim 1 , wherein the serpentine interconnects are configured to be flexible and permit bending in-plane and out-of-plane.

16. A deformable array of semiconductor devices comprising:
a plurality of islands arranged in an auxetic geometry so that the array exhibits a negative Poisson's ratio when loaded under tensile strain; and
a plurality of serpentine interconnects coupling the plurality of islands to one another, each having a first end which connects to one island and a second end which connects to an adjacent island and a plurality of bends therebetween,
wherein the islands and interconnects lie in the same plane in an unstretched condition,
wherein, in the unstretched condition, each interconnect couples, at its first end, to the one island near one corner of the one island, extends in a direction toward another corner of the one island, bends in the same plane to extend in the opposite direction to back towards the one corner of the one island, at least twice, and couples, at its second end, to the adjacent island, and
wherein a semiconductor device is formed within or on at least one of the islands and/or at least one of the serpentine interconnects.

17. The deformable array of semiconductor devices of claim 16 , wherein an active PN junction is incorporated into the top and/or sidewalls of the islands forming the semiconductor devices.

18. A method of fabricating a deformable array of semiconductor devices according to claim 16 , the method comprising:
providing a substrate comprising a SiO 2 layer over a Si layer;
etching the SiO 2 layer to form a SiO 2 hard mask that defines an auxetic geometry comprising the islands and the serpentine interconnects between the islands;
etching through the Si layer to define the islands and serpentine interconnects in accordance with the hard mask on the Si so that the array exhibits a negative Poisson's ratio when loaded under tensile strain; and
depositing at least one material onto the etched substrate to form at least one semiconductor device on the islands.

19. The method of fabricating a deformable array of semiconductor devices of claim 18 wherein the at least one material comprises at least one of metal, and one active semiconductor component.

20. The method of fabricating a deformable array of semiconductor devices of claim 18 wherein the depositing is performed by vapor phase deposition techniques, spin coating, or spray coating.

21. The method of fabricating a deformable array of semiconductor devices of claim 18 wherein the deposited materials form PN junctions in the islands.

22. The method of fabricating a deformable array of semiconductor devices of claim 21 wherein the PN junctions form solar cells.

23. The method of fabricating a deformable array of semiconductor devices of claim 22 wherein the depositing further comprises depositing materials on the serpentine interconnects to form additional PN junctions on the serpentine interconnects.

24. The method of fabricating a deformable array of semiconductor devices of claim 22 wherein PN junctions are formed on a sidewall of each island and/or each serpentine interconnect.

25. The method of fabricating a deformable array of semiconductor devices of claim 24 wherein the sidewall PN junctions create active solar areas in addition to the solar cells formed in the islands.

Assignees

• Ccdc Army Res Laboratory
• Us Army

Inventors

• Curtis Sabrina M
• Wang Haotian
• Anfinrud Gabriel P
• Randolph Alexander O
• Smith Gabriel L
• Lazarus Nathan S

Classifications

• H10F77/147

  Shapes of bodies · CPC title

• H10F71/121

  The active layers comprising only Group IV materials · CPC title

• H10F19/90 Primary

  Structures for connecting between photovoltaic cells, e.g. interconnections or insulating spacers (between thin-film photovoltaic cells on a single substrate H10F19/35) · CPC title

• H10F19/10 Primary

  comprising photovoltaic cells in arrays in a single semiconductor substrate, the photovoltaic cells having vertical junctions or V-groove junctions · CPC title

• H01L31/05 Primary

  Electricity · mapped topic