Memory device having volatile and non-volatile memory cells

Patent metadata

Field	Value
Publication number	US-11922984-B2
Application number	US-202217949305-A
Country	US
Kind code	B2
Filing date	Sep 21, 2022
Priority date	Jun 4, 2019
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

First claim

What is claimed is:

1. A memory device, comprising:
a first memory cell array including first memory cells having volatility;
a second memory cell array including second memory cells having non-volatility, each of the second memory cells having a height smaller than a height of each of the first memory cells in a direction perpendicular to a top surface of a substrate in which the first memory cells and the second memory cells are disposed;
transfer switches between the first memory cells and the second memory cells; and
a controller configured to turn on the transfer switches, read data of at least one of the first memory cells, and store the data in at least one of the second memory cells.

2. A method of manufacturing a memory device, the method comprising:
forming isolation layers in a first region and a second region of a substrate to define first and second active regions in the first and second regions, respectively;
removing at least a portion of the first active regions and at least a portion of the second active regions to form trenches;
forming first gate insulating layers in the trenches of the first active regions;
forming second gate insulating layers in the trenches of the second active regions, a material of the second gate insulating layers being different from a material of the first gate insulating layers;
forming gate structures in the trenches of the first and second active regions, such that a first memory cell array with first memory cells having volatility is formed in the first active region and a second memory cell array with second memory cells having non-volatility is formed in the second active region, each of the second memory cells having a height smaller than a height of each of the first memory cells in a direction perpendicular to a top surface of the substrate;
forming transfer switches between the first memory cells and the second memory cells; and
forming a controller configured to turn on the transfer switches, read data of at least one of the first memory cells, and store the data in at least one of the second memory cells.

3. The method as claimed in claim 2 , wherein a dielectric constant of the second gate insulating layers is higher than a dielectric constant of the first gate insulating layers.

4. The method as claimed in claim 2 , further comprising forming capacitors connected to the first active regions.

5. The method as claimed in claim 2 , wherein forming the transfer switches includes forming the transfer switches in a third region between the first region and the second region, each of the transfer switches including a third active region and a third gate structure, the third active region being connected to the gate structures of the first region and the second region.

6. A method of manufacturing a memory device, the method comprising:
forming a first gate structure embedded in a substrate, a first active region including a first channel region adjacent to the first gate structure, and a capacitor connected to the first active region and extended in a direction perpendicular to a top surface of the substrate, such that a first memory cell having volatility is formed in the first active region;
forming an interlayer insulating layer to cover the capacitor;
forming a second gate structure on the interlayer insulating layer;
forming a ferroelectric layer to cover the second gate structure; and
forming a second channel region, including an indium-gallium-zinc oxide, and a second active region, connected to the second channel region, on the ferroelectric layer, such that a second memory cell having non-volatility is formed in the second active region, the second memory cell having a height smaller than a height of the first memory cell in a direction perpendicular to a top surface of the substrate;
forming a transfer switch between the first and second memory cells; and
forming a controller configured to turn on the transfer switch, read data of the first memory cell, and store the data in the second memory cell.

7. The memory device as claimed in claim 1 , wherein the second memory cells are at a same height as the transfer switches.

8. The memory device as claimed in claim 7 , wherein the first memory cells extend above the second memory cells.

9. The memory device as claimed in claim 1 , wherein:
each of the first memory cells includes a capacitor connected to a corresponding one of the transfer switches, the capacitor extending in the direction perpendicular to the top surface of the substrate, and
each of the second memory cells does not include a capacitor.

10. The memory device as claimed in claim 1 , wherein the transfer switches share a single transfer gate structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Minhee
• Song Woobin
• Park Hyunmog
• Lee Sangkil

Classifications

• G11C11/005 Primary

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G11C11/223

  using MOS with ferroelectric gate insulating film · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• H10B12/33

  the capacitor extending under the transistor · CPC title