Semiconductor storage device comprising peripheral circuit, shielding layer, and memory cell array

Patent metadata

Field	Value
Publication number	US-10170486-B2
Application number	US-201615083364-A
Country	US
Kind code	B2
Filing date	Mar 29, 2016
Priority date	Sep 21, 2011
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.

First claim

What is claimed is:

1. A semiconductor storage device comprising:
a first transistor;
a conductive film over the first transistor; and
a plurality of second transistors each comprising a channel region,
wherein a channel region of the first transistor comprises silicon,
wherein each of the plurality of channel regions of second transistors comprises an oxide semiconductor, and
wherein entirety of the plurality of second transistors overlaps with the conductive film.

2. The semiconductor storage device according to claim 1 , wherein the first transistor is formed by utilizing a semiconductor substrate.

3. The semiconductor storage device according to claim 1 , further comprising a second conductive film over the plurality of second transistors and a plurality of third transistors over the second conductive film.

4. The semiconductor storage device according to claim 1 , wherein the conductive film is configured to be supplied with a ground potential.

5. The semiconductor storage device according to claim 1 , wherein the first transistor is electrically connected to at least one of the plurality of second transistors through a contact plug comprising a same layer as the conductive film.

6. A semiconductor storage device comprising:
a first transistor;
a first conductive film over the first transistor;
a plurality of second transistors over the first conductive film;
a second conductive film over the plurality of second transistors; and
a plurality of third transistors over the second conductive film,
wherein entirety of the plurality of second transistors overlaps with the first conductive film, and
wherein entirety of the plurality of third transistors overlaps with the second conductive film.

7. The semiconductor storage device according to claim 6 , wherein the first transistor is formed by utilizing a semiconductor substrate.

8. The semiconductor storage device according to claim 6 , wherein the first conductive film is configured to be supplied with a ground potential.

9. The semiconductor storage device according to claim 6 , wherein the first transistor is electrically connected to at least one of the plurality of second transistors through a contact plug comprising a same layer as the first conductive film.

Assignees

• Semiconductor Energy Lab

Inventors

• Atsumi Tomoaki
• Okuda Takashi

Classifications

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title

• H10W20/071 Primary

  of dielectric parts thereof · CPC title

• H10B41/70

  the floating gate being an electrode shared by two or more components · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title