Integrated circuits as a service

Patent metadata

Field	Value
Publication number	US-11922101-B2
Application number	US-202318123422-A
Country	US
Kind code	B2
Filing date	Mar 20, 2023
Priority date	Aug 2, 2018
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

First claim

What is claimed is:

1. A method comprising:
receiving a design parameters data structure, wherein the design parameters data structure includes values of design parameters of an integrated circuit design;
automatically generating a register-transfer level data structure and a physical design data structure for an integrated circuit based on the design parameters data structure, wherein the physical design data structure encodes a layout of the integrated circuit;
automatically generating a test plan for an integrated circuit based on the design parameters data structure; and
automatically invoking tests for the integrated circuit based on the test plan, the register-transfer level data structure, and the physical design data structure to obtain a set of test results.

2. The method of claim 1 , comprising:
automatically generating documentation for the integrated circuit based on the register-transfer level data structure.

3. The method of claim 2 , wherein generating documentation for the integrated circuit comprises:
parsing the register-transfer level data structure for the integrated circuit to identify applicable portions of a documentation framework;
generating snippets of documentation based on the applicable portions identified;
assembling the snippets into a dictionary;
instantiating a document from a template; and
merging references to the dictionary with the document.

4. The method of claim 1 , comprising:
automatically generating a field programmable gate array emulation data structure for the integrated circuit based on the register-transfer level data structure.

5. The method of claim 4 , comprising:
invoking a test using a field programmable gate array, programmed based on the field programmable gate array emulation data structure, to obtain an emulation result, wherein the field programmable gate array is operating on a cloud server.

6. The method of claim 1 , comprising:
transmitting a physical design specification based on the physical design data structure to a server to invoke manufacturing of the integrated circuit.

7. The method of claim 6 , wherein the physical design specification includes designs for multiple independent integrated circuits, including the integrated circuit, and comprising:
allocating mask area to the multiple independent integrated circuits based on a production plan; and
performing design rule checks on the physical design specification.

8. The method of claim 6 , comprising:
manufacturing the integrated circuit;
installing the integrated circuit in a system configured to operate the integrated circuit responsive to commands received via communications with a cloud server; and
transmitting a login for accessing and controlling the integrated circuit.

9. The method of claim 1 , comprising:
updating the design parameters data structure based on the test results.

10. The method of claim 1 , comprising:
generating the design parameters data structure based on input received via a web application that displays an auto-updating block diagram of a template design reflecting changes to values of the design parameters of the integrated circuit.

11. A system comprising:
a memory; and
a processor, wherein the memory includes instructions executable by the processor to cause the system to:
receive a design parameters data structure, wherein the design parameters data structure includes values of design parameters of an integrated circuit design;
automatically generate a register-transfer level data structure and a physical design data structure for an integrated circuit based on the design parameters data structure, wherein the physical design data structure encodes a layout of the integrated circuit;
automatically generate a test plan for an integrated circuit based on the design parameters data structure; and
automatically invoke tests for the integrated circuit based on the test plan, the register-transfer level data structure, and the physical design data structure to obtain a set of test results.

12. The system of claim 11 , wherein the memory includes instructions executable by the processor to cause the system to:
automatically generate a field programmable gate array emulation data structure for the integrated circuit based on the register-transfer level data structure; and
invoke a test using a field programmable gate array, programmed based on the field programmable gate array emulation data structure, to obtain an emulation result, wherein the field programmable gate array is operating on a cloud server.

13. The system of claim 11 , wherein the memory includes instructions executable by the processor to cause the system to:
transmit a physical design specification based on the physical design data structure to a server to invoke manufacturing of the integrated circuit.

14. The system of claim 11 , wherein the memory includes instructions executable by the processor to cause the system to:
update the design parameters data structure based on the test results.

15. The system of claim 11 , wherein the memory includes instructions executable by the processor to cause the system to:
generate the design parameters data structure based on input received via a web application that displays an auto-updating block diagram of a template design reflecting changes to values of the design parameters of the integrated circuit.

16. A system comprising:
a web application server configured to generate a design parameters data structure based on input received, wherein the design parameters data structure includes values of design parameters of an integrated circuit design, configured to display an auto-updating block diagram of a template design reflecting changes to values of the design parameters of the integrated circuit, wherein the auto-updating block diagram is updated in response to changes made to the design parameter values using design knobs displayed by the web application server, and configured to issue a command to build the integrated circuit design; and
a controller configured to, responsive to the command to build the integrated circuit design, access the design parameters data structure, invoke a register-transfer level service module with the design parameters data structure to obtain a register-transfer level data structure, invoke a verification service module to obtain a test plan, and invoke tests for the integrated circuit based on the test plan and the register-transfer level data structure to obtain a set of test results.

17. The system of claim 16 , wherein the controller is configured to:
invoke a documentation service module with the register-transfer level data structure to obtain documentation for the integrated circuit based on the register-transfer level data structure.

18. The system of claim 16 , wherein the controller is configured to:
invoke a software development kit service module configured to generate a software development kit based on the register-transfer level data structure;
invoke a field programmable gate array service module configured to generate a field programmable gate array emulation data structure for the integrated circuit based on the register-transfer level data structure and the software development kit; and
invoke a test using a field programmable gate array, programmed based on the field programmable gate array emulation data structure, to obtain an emulation result, wherein the field programmable gate array is operating on a cloud server.

19. The system of claim 16 , wherein the controller is

Assignees

• Sifive Inc

Inventors

• Lee Yunsup
• Xia Richard
• Pappas Derek
• Nugent Mark
• Cook Henry
• Terpstra Wesley Waylon
• Chen Pin Hung

Classifications

• G06F30/20 Primary

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/31 Primary

  Design entry, e.g. editors specifically adapted for circuit design · CPC title

• G06F30/32 Primary

  Circuit design at the digital level (reconfigurable circuits G06F30/34) · CPC title

• G06F2115/02

  System on chip [SoC] design · CPC title