Block management in non-volatile memory system with non-blocking control sync system

Patent metadata

Field	Value
Publication number	US-9817593-B1
Application number	US-201615207212-A
Country	US
Kind code	B1
Filing date	Jul 11, 2016
Priority date	Jul 11, 2016
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

In a non-volatile memory system, the controller maintains in its volatile memory two free block lists for the assignment of memory circuit blocks when writing user and system data. Copies of the free block lists are maintained in the non-volatile memory. While allocating blocks from a first of the free block lists, the controller can update a second of the free block lists as part of a control sync operation preparing control data stored in non-volatile memory. This allows the memory system to operate in a non-blocking manner during the control sync. Once the second free block lists is prepared and the control sync completed, the second block can subsequently be used for block allocations and a control sync operation can be done to update the first block.

First claim

It is claimed:

1. A method of operating a non-volatile memory system, comprising:
storing data, including user and control data, in a non-volatile memory circuit having a plurality of non-volatile memory cells formed as a plurality of multi-cell blocks; and
managing the storage of data on the memory circuit by a controller, the managing comprising:
maintaining in volatile memory of two or more free block lists, the two or more free block lists being formed of blocks available for the writing of data;
maintaining copies of the two of more free block lists in the non-volatile memory;
allocating blocks from a first free block list of the two or more free block lists;
while allocating the blocks from the first free block list, performing a synchronizing operation for a second free block list of the two or more free block lists, the synchronizing operation comprising:
updating the second free block list; and
preparing control data related to the updating of the second free block list; and

allocating blocks from the updated second free block list and discontinuing allocating the blocks from the first free block list after the synchronizing operation is completed.

2. The method of claim 1 , further comprising:
receiving a notification that the synchronizing operation for the second free block list is completed;
storing the control data related to the updating of the second free block list in the non-volatile memory; and
in response to the notification, allocating the blocks from the updated second free block list.

3. The method of claim 1 , wherein updating the second free block list comprises:
adding one or more blocks without valid data; and
removing the blocks allocated from the first free block list.

4. The method of claim 3 , wherein adding the one or more blocks without valid data comprises:
selecting blocks from a pool of available blocks including previously allocated, but subsequently released blocks.

5. The method of claim 4 , wherein updating the second free block list comprises:
replacing the one or more blocks with a corresponding number of one or more blocks from the pool of available blocks based on characteristics of the one or more blocks being replaced and the one or more blocks from the pool of available blocks used as replacements.

6. The method of claim 1 , wherein the two or more free block lists are allowed to have common elements.

7. The method of claim 1 , further comprising:
during an initialization process, reestablishing the two or more free block lists maintained in the volatile memory from the copies of the two or more free block lists from the non-volatile memory into the volatile memory.

8. The method of claim 1 , wherein the managing is implemented as firmware executed by the controller.

9. The method of claim 1 , wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device in which the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

10. A controller for a non-volatile memory system, comprising:
a volatile memory;
logic circuitry configured to manage the storage of data on a non-volatile memory circuit having a plurality of non-volatile memory cells formed as a plurality of multi-cell blocks, wherein managing of the storage of data on the non-volatile memory circuit comprises:
maintaining in volatile memory of two or more free block lists, the two or more free block lists being formed of blocks available for the writing of data;
maintaining copies of the two or more free block lists in the non-volatile memory;
allocating blocks from a first free block list of the two or more free block lists;
while allocating the blocks from the first free block list, performing a synchronizing operation for a second free block list of the two or more free block lists, the synchronizing operation comprising:
updating the second free block list; and
preparing control data related to the updating of the second free block list; and

allocating blocks from the updated second free block list and discontinuing allocating the blocks from the first free block list after the synchronizing operation is completed.

11. The controller of claim 10 , the managing further comprising:
receiving a notification that the synchronizing operation for the second free block list is completed;
storing the control data related to the updating of the second free block list in the non-volatile memory; and
in response to the notification, allocating the blocks from the updated second free block list.

12. The controller of claim 10 , wherein updating the second free block list comprises:
adding one or more blocks without valid data; and
removing the blocks allocated from the first free block list.

13. The controller of claim 10 , wherein during an initialization process, the logic circuitry reestablishes the two or more free block lists maintained in the volatile memory from the copies of the two or more free block lists from the non-volatile memory into the volatile memory.

14. The controller of claim 10 , wherein the managing is implemented as firmware executed by the controller.

15. The controller of claim 10 , wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device in which the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

16. A non-volatile memory system, comprising:
a non-volatile memory circuit having a plurality of non-volatile memory cells formed as a plurality of multi-cell blocks; and
a controller, including:
a volatile memory;
logic circuitry configured to manage the storage of data on a non-volatile memory circuit having a plurality of non-volatile memory cells formed as a plurality of multi-cell blocks, wherein managing of the storage of data on the non-volatile memory circuit includes:
maintaining in volatile memory of two or more free block lists, the two or more free block lists being formed of blocks available for the writing of data;
maintaining copies of the two or more block lists in the non-volatile memory;
allocating blocks from a first free block list of the two or more free block lists;
while allocating the blocks from the first free block list, performing a synchronizing operation for a second free block list of the two or more free block lists, the synchronizing operation including:
updating the second free block list; and
preparing control data related to the updating of the second free block list and

allocating blocks from the updated second free block list and discontinuing allocating the blocks from the first free block list after the synchronizing operation is completed.

17. The non-volatile memory system of claim 16 , the managing further comprising:
receiving a notification that the synchronizing operation for the second free block list is completed;
storing the control data related to the updating of the second free block list in the non-volatile memory; and
in response to the notification, allocating the blocks from the updated second free block list.

18. The non-volatile memory system of claim 16 , wherein updating the second free block list comprises:
adding one or more blocks without valid data; and
removing the blocks allocated from the first free block list.

19. The non-volatile memory system of claim 16 , wherein during an initialization process, the logic circuitry reestablishes the two or more free block list

Assignees

• Sandisk Technologies Llc

Inventors

• Inbar Karin
• Lev Einat
• Yonin Michael

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F3/065

  Replication mechanisms · CPC title

• G11C14/00

  Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title