Method and system for packing optimization of semiconductor devices

Patent metadata

Field	Value
Publication number	US-11916033-B2
Application number	US-202217588525-A
Country	US
Kind code	B2
Filing date	Jan 31, 2022
Priority date	Aug 10, 2016
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

First claim

What is claimed:

1. An apparatus, comprising:
a substrate having a first surface and a second surface opposite the first surface, wherein the second surface comprises at least eight regions bounded by first radial reference lines that radiate from a radial origin at the second surface and define an acute central angle of each region at the radial origin; and
first interconnects arranged in each region, wherein each first interconnect includes a minor axis and a major axis greater than its respective minor axis, and wherein the major axis of each first interconnect in its respective region is parallel to a second radial reference line that radiates from the radial origin and through the respective region;
wherein each of the first interconnects lies on the second radial reference line that radiates through its respective region;
wherein each region includes second interconnects not lying on the second radial reference line that radiates through its respective region; and
wherein a major axis of each second interconnect is parallel to the second radial reference line that radiates through its respective region.

2. The apparatus of claim 1 , comprising third interconnects, wherein:
the second surface of the substrate comprises a first perimeter edge;
each third interconnect comprises a minor axis and a major axis greater than its respective minor axis; and
each third interconnect is arranged along the first perimeter edge of the second surface such that the major axis of each third interconnect is parallel to the first perimeter edge of the second surface.

3. The apparatus of claim 1 , comprising third interconnects, wherein:
the second surface of the substrate comprises a perimeter edge with one or more corners;
each third interconnect comprises a minor axis and a major axis greater than its respective minor axis; and
each third interconnect is arranged along a first corner of the one or more corners such that the major axis of each third interconnect is perpendicular to a third radial reference line that radiates from the radial origin and through the first corner of the one or more corners.

4. The apparatus of claim 1 , wherein:
the substrate comprises a semiconductor die; and
the first interconnects are connected to circuitry of the semiconductor die.

5. The apparatus of claim 1 , comprising:
a semiconductor die connected to the first surface of the substrate; and
wherein the first interconnects are connected to circuitry of the semiconductor die via the substrate.

6. The apparatus of claim 1 , wherein each first interconnect is elliptical.

7. The apparatus of claim 1 , wherein each region is an isosceles wedge-shaped region.

8. The apparatus of claim 1 , wherein every interconnect in a respective region comprises a major axis that is parallel to the second radial reference line radiating through the respective region.

9. The apparatus of claim 1 , wherein each second radial reference line bisects the acute central angle of the region through which the respective second radial reference line radiates.

10. The apparatus of claim 1 , wherein:
each of the first interconnects lies on a first reference line that is parallel to the second radial reference line radiating through its respective region; and
each region includes third interconnects that lie on a third reference line that is parallel to the second radial reference line radiating through its respective region; and
a major axis of each third interconnect is parallel to the third reference line on which its respective third interconnect lies.

11. The apparatus of claim 1 , wherein the acute central angles of the regions sum to 360°.

12. The apparatus of claim 1 , wherein the major axis for each interconnect of the majority of the interconnects in each region is a same length.

13. The apparatus of claim 2 , wherein:
the substrate comprises a semiconductor die; and
the first interconnects are connected to circuitry of the semiconductor die.

14. The apparatus of claim 2 , wherein each interconnect is elliptical.

15. The apparatus of claim 2 , wherein every interconnect in a respective region comprises a major axis that is parallel to the second radial reference line radiating through the respective region.

16. The apparatus of claim 2 , wherein:
each of the first interconnects lies on a first reference line that is parallel to the second radial reference line radiating through its respective region; and
each region includes third interconnects that lie on a third reference line that is parallel to the second radial reference line radiating through its respective region; and
a major axis of each third interconnect is parallel to the third reference line on which its respective third interconnect lies.

17. The apparatus of claim 3 , comprising:
a semiconductor die connected to the first surface of the substrate; and
wherein first interconnects are connected to circuitry of the semiconductor die via the substrate.

18. The apparatus of claim 3 , wherein each second radial reference line bisects the acute central angle of the region through which the respective second radial reference line radiates.

19. A method comprising:
providing a substrate having a first surface and a second surface opposite the first surface; and
arranging interconnects on the second surface of the substrate such that the interconnects include at least one of:
first interconnects arranged in each first region of at least eight first regions of the second surface that are bounded by first radial reference lines radiating from a radial origin at the second surface and defining an acute central first angle of each first region at the radial origin, wherein each first interconnect includes a minor axis and a major axis greater than its respective minor axis, wherein the major axis of each first interconnect in its respective first region is parallel to a second radial reference line that radiates from the radial origin and through the respective first region, wherein each of the first interconnects lies on the second radial reference line that radiates through its respective region; wherein each region includes second interconnects not lying on the second radial reference line that radiates through its respective region, and wherein a major axis of each second interconnect is parallel to the second radial reference line that radiates through its respective region; or
second interconnects arranged in each second region of the second surface bounded by third radial reference lines that radiate from the radial origin at the second surface and define an acute central second angle of each second region at the radial origin, wherein the acute central second angles of the second regions sum to 360°, wherein each interconnect of a majority of the second interconnects includes a minor axis and a major axis greater than its respective minor axis, and wherein the major axis of each interconnect of the majority is parallel to a fourth radial reference line that radiates from the radial origin and through the respective second region.

Assignees

• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Rinne Glenn
• Richter Daniel

Classifications

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/237

  Multiple bump connectors having different shapes · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/234

  Cross-sectional shape, i.e. in side view · CPC title