Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-11910597-B2
Application number	US-202217734410-A
Country	US
Kind code	B2
Filing date	May 2, 2022
Priority date	Mar 6, 2019
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

First claim

We claim:

1. An integrated assembly, comprising:
a lower carrier-sink-structure;
first comparative digit lines over the lower carrier-sink-structure;
first source/drain regions over the first comparative digit lines and being coupled with the first comparative digit lines;
vertically-extending first pillars over the first source/drain regions; each of the first pillars comprising a first transistor body region and a second source/drain region;
capacitors coupled with the second source/drain regions;
vertically-extending second pillars over the capacitors; each of the second pillars comprising a third source/drain region and a second transistor body region over the third source/drain region; the third source/drain regions being coupled with capacitor nodes;
fourth source/drain regions over the second transistor body regions;
second comparative digit lines over the fourth source/drain regions and being coupled with the fourth source/drain regions; individuals of the first comparative digit lines being paired with individuals of the second comparative digit lines in a plurality of first/second comparative digit line sets; the first comparative digit lines and second comparative digit lines of each of the first/second comparative digit line sets extending to a sense amplifier configured to compare electrical properties of the first and second comparative digit lines within the first/second comparative digit line set;
an upper carrier-sink-structure over the second digit lines;
first extensions extending from the lower carrier-sink-structure to the first transistor body regions; the first extensions being configured to drain excess carriers from the first transistor body regions to the lower carrier-sink-structure;
second extensions extending from the upper carrier-sink-structure to the second transistor body regions; the second extensions being configured to drain excess carriers from the second transistor body regions to the upper carrier-sink-structure; and
gates having components adjacent the first and second transistor body regions.

2. The integrated assembly of claim 1 wherein the upper and lower carrier-sink-structures are coupled to a voltage source configured to provide a reference voltage to the upper and lower carrier-sink-structures.

3. The integrated assembly of claim 1 wherein the capacitors, first pillars and second pillars are together comprised by two-transistor-one-capacitor memory (2T-1C) memory cells of a memory array.

4. The integrated assembly of claim 3 wherein the memory array is within a tier; the tier being within a vertically-stacked arrangement of tiers and being over at least one other of the tiers within the vertically-stacked arrangement.

5. The integrated assembly of claim 1 wherein the upper and lower carrier-sink-structures are p-type.

6. The integrated assembly of claim 1 wherein the upper and lower carrier-sink-structures are n-type.

7. The integrated assembly of claim 1 wherein the first extensions directly contact the first transistor body regions; and wherein the second extensions directly contact the second transistor body regions.

8. The integrated assembly of claim 1 wherein the first extensions are spaced from the first transistor body regions by first intervening insulative regions; and wherein the second extensions are spaced from the second transistor body regions by second intervening insulative regions.

Assignees

• Micron Technology Inc

Inventors

• Karda Kamal M
• Liu Haitao
• Ramaswamy Durai Vishak Nirmal
• Gao Yunfei
• Tang Sanh D
• Pandey Deepak Chandra

Classifications

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025 Primary

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title