Transistors, memory cells and semiconductor constructions

Patent metadata

Field	Value
Publication number	US-9590066-B2
Application number	US-201614991792-A
Country	US
Kind code	B2
Filing date	Jan 8, 2016
Priority date	Nov 20, 2012
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

First claim

We claim:

1. A semiconductor construction, comprising:
a silicon-containing semiconductor base;
a gate extending into the silicon-containing semiconductor base; a first region of the silicon-containing semiconductor base adjacent the gate being a conductively-doped source region, and a second region of the silicon-containing semiconductor base adjacent the gate and spaced from the first region being a conductively-doped drain region;
a gate dielectric comprising a first segment between the conductively-doped source region and the gate, a second segment between the conductively-doped drain region and the gate, and a third segment between the first and second segments;
wherein at least a portion of the gate dielectric comprises ferroelectric material;
wherein the gate dielectric, along a cross-section, is configured as an upwardly-opening container having the gate therein;
wherein the first segment of the gate dielectric comprises a first leg of the upwardly-opening container, the second segment of the gate dielectric comprises a second leg of the upwardly-opening container, and the third segment of the gate dielectric comprises a bottom of the upwardly-opening container;
wherein at least a portion of the gate dielectric comprises a first material as an outer boundary of the upwardly-opening container and which is directly against the silicon-containing semiconductor base, and comprises a second material between the first material and the gate;
wherein the second material is the ferroelectric material;
wherein the first material is a non-ferroelectric material; and
wherein the ferroelectric material is only within the first segment.

2. A semiconductor construction, comprising:
a silicon-containing semiconductor base;
a gate extending into the silicon-containing semiconductor base; a first region of the silicon-containing semiconductor base adjacent the gate being a conductively-doped source region, and a second region of the silicon-containing semiconductor base adjacent the gate and spaced from the first region being a conductively-doped drain region;
a gate dielectric comprising a first segment between the conductively-doped source region and the gate, a second segment between the conductively-doped drain region and the gate, and a third segment between the first and second segments;
wherein at least a portion of the gate dielectric comprises ferroelectric material;
wherein the gate dielectric, along a cross-section, is configured as an upwardly-opening container having the gate therein;
wherein the first segment of the gate dielectric comprises a first leg of the upwardly-opening container, the second segment of the gate dielectric comprises a second leg of the upwardly-opening container, and the third segment of the gate dielectric comprises a bottom of the upwardly-opening container;
wherein at least a portion of the gate dielectric comprises a first material as an outer boundary of the upwardly-opening container and which is directly against the silicon-containing semiconductor base, and comprises a second material between the first material and the gate;
wherein the second material is the ferroelectric material;
wherein the first material is a non-ferroelectric material; and
wherein the ferroelectric material is only within the third segment.

3. A semiconductor construction, comprising:
a silicon-containing semiconductor base;
a gate extending into the silicon-containing semiconductor base; a region of the silicon-containing semiconductor base on one side of the gate being a conductively-doped source region, and a region of the silicon-containing semiconductor base on an opposing side of the gate relative to said one side being a conductively-doped drain region; the conductively-doped drain region being more heavily doped than the conductively-doped source region;
a gate dielectric comprising a first segment between the conductively-doped source region and the gate, a second segment between the conductively-doped drain region and the gate, and a third segment between the first and second segments;
wherein the gate dielectric, along a cross-section, is configured as an upwardly-opening container having the gate therein; wherein the first segment of the gate dielectric comprises a first leg of the upwardly-opening container, wherein the second segment of the gate dielectric comprises a second leg of the upwardly-opening container, and wherein the third segment of the gate dielectric comprises a bottom of the upwardly-opening container;
the gate dielectric comprising non-ferroelectric material directly against ferroelectric material, with the non-ferroelectric material being a boundary of the upwardly-opening container directly against the silicon-containing semiconductor base; and
wherein the non-ferroelectric material is thicker along the bottom of the upwardly-opening container than along the first and second legs of the upwardly-opening container.

4. The semiconductor construction of claim 3 wherein the non-ferroelectric material comprises one or both of silicon dioxide and silicon nitride.

5. The semiconductor construction of claim 3 further comprising a capacitor electrically coupled to the conductively-doped drain region.

6. The semiconductor construction of claim 3 wherein the conductively-doped source region comprises a dopant gradient in which dopant concentration is lighter in a location relatively deep within the conductively-doped source region as compared to a location relatively shallow within the conductively-doped source region.

7. The semiconductor construction of claim 3 wherein the ferroelectric material comprises one or more of Hf, Zr, Si, O, Y, Ba, Mg and Ti.

8. The semiconductor construction of claim 3 wherein the non-ferroelectric material comprises a thickness within the first and second segments within a range of from about 10 angstroms to about 20 angstroms, and comprises a thickness within the third segment within a range of from about 25 angstroms to about 50 angstroms.

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy Durai Vishak
• Prall Kirk D
• Kinney Wayne

Classifications

• G11C14/0027

  and the nonvolatile element is a ferroelectric element · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title

• H01L45/1233

  Electricity · mapped topic

• H01L29/78391

  Electricity · mapped topic