Contact formation for vertical field effect transistors

Patent metadata

Field	Value
Publication number	US-11908944-B2
Application number	US-202117447904-A
Country	US
Kind code	B2
Filing date	Sep 16, 2021
Priority date	Sep 16, 2021
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A vertical field effect transistor includes a top source/drain region in contact with a top portion of a channel fin extending perpendicularly from a semiconductor substrate, a bottom source/drain region is disposed above the semiconductor substrate and on opposite sidewalls of a bottom portion of the channel fin, a metal gate surrounding the channel fin is separated from the top source/drain region by a top spacer and from the bottom source/drain region by a bottom spacer, the metal gate and the top spacer are in contact with an adjacent first interlevel dielectric layer. A silicide layer is directly above an uppermost surface of the top source/drain region, and a nitride layer is directly above an uppermost surface of the silicide layer. A top source/drain contact, having a size that is substantially less than a length of the channel fin, extends until an uppermost surface of the nitride layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a channel fin extending perpendicularly from a semiconductor substrate;
a top source/drain region in contact with a top portion of the channel fin,
the top source/drain region including a bottom portion abutted by a first side of a top spacer and a top portion extending outwards from the top spacer,
a second side of the top spacer, opposing the first side, being in contact with a first interlevel dielectric layer;
a bottom source/drain region disposed above the semiconductor substrate and in contact with opposite sidewalls of a bottom portion of the channel fin;
a metal gate stack in contact with a central portion of the channel fin, the metal gate stack being separated from the top source/drain region by the top spacer and from the bottom source/drain region by a bottom spacer;
a silicide layer disposed above and in direct contact with opposite sidewalls of the top portion of the top source/drain region; and
a nitride layer disposed above and in direct contact with an uppermost surface of the silicide layer,
a topmost surface of the top spacer being in contact with opposing ends of the silicide layer and the nitride layer.

2. The semiconductor structure of claim 1 , further comprising:
a top source/drain contact extending through a second interlevel dielectric layer until an uppermost surface of the nitride layer;
a bottom source/drain contact extending through the first interlevel dielectric layer and the second interlevel dielectric layer until an uppermost surface of the bottom source/drain region; and
a gate contact extending through the first interlevel dielectric layer and the second interlevel dielectric layer until an uppermost surface of the metal gate stack.

3. The semiconductor structure of claim 1 , wherein the top portion of the top source/drain region extending outwards from the top spacer comprises a diamond-shaped epitaxial region above which the silicide layer is formed, the top spacer abutting the bottom portion of the top source/drain region including two vertical sections with respect to the semiconductor substrate disposed on opposite sides of the bottom portion of the top source/drain region and a horizontal section with respect to the semiconductor substrate disposed on opposite sides of the channel fin.

4. The semiconductor structure of claim 1 , wherein the silicide layer comprises a titanium silicide layer formed from a titanium liner during a silicide anneal process.

5. The semiconductor structure of claim 4 , wherein the nitride layer comprises a titanium nitride layer formed from the titanium liner during a nitridation process.

6. The semiconductor structure of claim 1 , wherein the top source/drain region is p-type doped for providing a P-FET device.

7. The semiconductor structure of claim 6 , further comprising:
a masking layer disposed above the first interlevel dielectric layer and above a first portion of the nitride layer not covered by the top source/drain contact, a second portion of the nitride layer being in contact with the top source/drain contact, the masking layer being in contact, on a side opposing the nitride layer, with the second interlevel dielectric layer.

8. The semiconductor structure of claim 1 , wherein the top source/drain region is n-type doped for providing a N-FET device.

Assignees

• IBM

Inventors

• Wu Heng
• Yu Lan
• Choi Samuel Sung Shik
• Xie Ruilong

Classifications

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H10D30/025 Primary

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title