Method for forming low parasitic capacitance source and drain contacts

Patent metadata

Field	Value
Publication number	US-9768062-B1
Application number	US-201615276748-A
Country	US
Kind code	B1
Filing date	Sep 26, 2016
Priority date	Jun 16, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A method for forming a low parasitic capacitance contact to a source-drain structure of a fin field effect transistor device. In some embodiments the method includes etching a long trench down to the source-drain structure, the trench being sufficiently long to extend across all the of source-drain regions of the device. A conductive layer is formed on the source-drain structure, and the trench is filled with a first fill material. A second, narrower trench is opened along a portion of the length of the first trench, and filled with a second fill material. The first fill material may be conductive, and may form the contact. If the first fill material is not conductive, a third trench may be opened, in the portion of the first trench not filled with the second fill material, and filled with a conductive material, to form the contact.

First claim

What is claimed is:

1. A method for fabricating a source-drain contact for a fin field effect transistor (FinFET) device having a plurality of fins, and a source-drain structure, the method comprising:
etching a first trench to the source-drain structure, the first trench having a first length in a first direction,
forming a first conductive layer in the first trench, on the source-drain structure;
forming an etch-stop layer in the first trench, on the first conductive layer;
filling the first trench with a first fill material;
forming a mask over a first portion of the first fill material, the mask not extending over a second portion of the first fill material;
etching, with an anisotropic etch, the second portion of the first fill material to form a second trench having a second length, less than the first length, in the first direction; and
filling the second trench with a second fill material, the second fill material being a dielectric.

2. The method of claim 1 , wherein the source-drain structure comprises a plurality of source-drain regions, each of the source-drain regions corresponding to one of the plurality of fins, wherein the first conductive layer overlaps a portion of each of the source-drain regions.

3. The method of claim 1 , wherein the first fill material comprises, as a major component, a semiconductor.

4. The method of claim 3 , wherein the first fill material comprises, as a major component, a semiconductor selected from the group consisting of: silicon, silicon-germanium, germanium, and combinations thereof.

5. The method of claim 1 , wherein the etch-stop layer comprises, as a major component, an oxide.

6. The method of claim 5 , wherein the etch-stop layer comprises, as a major component, an oxide selected from the group consisting of: silicon dioxide, aluminum oxide, and combinations thereof.

7. The method of claim 1 , wherein the first fill material comprises, as a major component, tungsten.

8. The method of claim 7 , wherein the etch-stop layer comprises, as a major component, a conductor.

9. The method of claim 1 , further comprising, after the filling a remainder of the first trench with the first fill material, planarizing a top surface of the first fill material.

10. The method of claim 1 , further comprising, after the etching, with the anisotropic etch, of the second portion of the first fill material, removing the mask.

11. The method of claim 1 , wherein the etching, with the anisotropic etch, of the second portion of the first fill material to form the second trench, comprises removing at least 90% of the first fill material in the second portion.

12. The method of claim 1 , further comprising, after the filling of the second trench with the second fill material, planarizing a top surface of the second fill material.

13. The method of claim 1 , further comprising, after the filling of the second trench with the second fill material, etching the first portion of the first fill material to form a third trench having a third length, less than the first length, in the first direction.

14. The method of claim 13 , further comprising, after the forming of the third trench, filling the third trench with a third fill material, the third fill material being a conductor.

15. The method of claim 14 , further comprising, after the forming of the third trench, and before the filling of the third trench with the third fill material, removing the etch-stop layer from a bottom of the third trench.

16. The method of claim 14 , wherein the third fill material comprises, as a major component, a conductor selected from the group consisting of: tungsten, cobalt, and combinations thereof.

17. The method of claim 14 , further comprising, after the forming of the third trench, and before the filling of the third trench with the third fill material, forming a conductive liner in the third trench.

18. The method of claim 17 , wherein:
the conductive liner comprises, as a major component, a material selected from the group consisting of: titanium, titanium nitride, and combinations thereof; and
the third fill material comprises, as a major component, a material selected from the group consisting of: tungsten, cobalt, and combinations thereof.

19. A method for fabricating a source-drain contact for a fin field effect transistor (FinFET) device having a plurality of fins, and a source-drain structure, the method comprising:
etching a first trench to the source-drain structure, the first trench having a first length in a first direction,
forming a first conductive layer in the first trench, on the source-drain structure;
forming an etch-stop layer in the first trench, on the first conductive layer;
filling the first trench with a first fill material;
forming a mask over a first portion of the first fill material, the mask not extending over a second portion of the first fill material;
etching, with an anisotropic etch, the second portion of the first fill material to form a second trench having a second length, less than the first length, in the first direction; and
filling the second trench with a second fill material, the second fill material being a dielectric,
wherein the first fill material comprises, as a major component, a material selected from the group consisting of: silicon, silicon-germanium, germanium, and combinations thereof, and
wherein the etch-stop layer comprises, as a major component, a material selected from the group consisting of: silicon dioxide, aluminum oxide, and combinations thereof.

20. A method for fabricating a source-drain contact for a fin field effect transistor (FinFET) device having a plurality of fins, and a source-drain structure, the method comprising:
etching a first trench to the source-drain structure, the first trench having a first length in a first direction,
forming a first conductive layer in the first trench, on the source-drain structure, the first conductive layer comprising:
as a major component, a material selected from the group consisting of titanium silicide, nickel silicide, cobalt silicide, and combinations thereof, or
a bi-layer comprising:
a lower sub-layer comprising, as a major component, a silicide; and
an upper layer, comprising, as a major component, a conductive nitride;

forming a conductive etch-stop layer in the first trench, on the first conductive layer, the forming of the etch-stop layer comprising a chemical vapor deposition process and/or a physical vapor deposition process, the etch-stop layer comprising, as a major component, cobalt;
forming a first liner in the first trench, the forming of the first liner comprising a chemical vapor deposition process and/or a physical vapor deposition process;
filling the first trench with a first fill material comprising, as a major component, tungsten;
forming a mask over a first portion of the first fill material, the mask not extending over a second portion of the first fill material;
etching, with an anisotropic etch, the second portion of the first fill material to form a second trench having a second length, less than the first length, in the first direction;
filling the second trench with a second fill material, the second fill material being a dielectric;
etching the first portion of the first fill material to form a third trench having a third length, less than the first length, in the first direction;
forming a second liner in the third trench, the forming of the second liner comprising a chemical vapor deposition process and/or a physical vapor deposit

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kittl Jorge A
• Seo David
• Oikawa Kota
• Changhwa Kim
• Sengupta Rwik
• Rodder Mark S

Classifications

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title