Single-gate field effect transistor and method for modulating the drive current thereof

Patent metadata

Field	Value
Publication number	US-11908935-B2
Application number	US-202017905367-A
Country	US
Kind code	B2
Filing date	May 26, 2020
Priority date	Mar 5, 2020
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

The present invention provides a single-gate field effect transistor device and a method for modulating the drive current thereof. The field effect transistor comprises an active layer, a source region and a drain region formed at two sides of the active layer, and a channel region located between the source region and the drain region. The field effect transistor device is configured as follows: when the transistor is turned off, a second channel of depletion-mode spontaneously forms in the channel region, and the second channel does not connect the source region and the drain region; when the transistor is turned on, the second channel and a first channel of the same polarity as the second channel are formed in the channel region; at least one of the first channel and the second channel injects carriers into the other channel so that current conduction occurs between the source and the drain and the carriers of the second channel contribute to the on-state current of the transistor.

First claim

What is claimed is:

1. A single-gate field effect transistor device, comprising an active layer, a source region and a drain region formed on two sides of the active layer, and a channel region located between the source region and the drain region; wherein the field effect transistor device is configured such that:
a depletion-mode second channel is spontaneously formed in the channel region when the transistor is turned off, the second channel does not connect the source region with the drain region; and
the second channel and a first channel which has the same polarity as the second channel are formed in the channel region when the transistor is turned on; wherein at least one of the first channel and the second channel injects carriers into the other channel such that the source region and the drain region are in electrical connection with each other, and carriers of the second channel contribute to the on-state current of the transistor.

2. The single-gate field effect transistor device according to claim 1 , wherein a superimposed part of a vertical projection of the first channel and a vertical projection of the second channel onto the channel region connects the source region with the drain region.

3. The single-gate field effect transistor device according to claim 2 , wherein the second channel is spaced from the source region and/or from the drain region.

4. The single-gate field effect transistor device according to claim 2 , wherein the first channel has a or has no space from the source region and the drain region.

5. The single-gate field effect transistor device according to claim 1 , wherein the number of carriers in the second channel is greater than that of carriers in the first channel when the transistor is subjected to a turn-on voltage; and the first channel is an enhancement channel.

6. The single-gate field effect transistor device according to claim 1 , wherein the field effect transistor device is a planar structure transistor or a vertical structure transistor.

7. The single-gate field effect transistor device of claim 1 , wherein the second channel is formed by the carriers introduced by doping on a surface of the channel region, said surface corresponding to one side of the second channel.

8. The single-gate field effect transistor device according to claim 7 , wherein an areal density of the carrier in the second channel is greater than the areal density of the carrier in the first channel when the turn-on voltage is applied to the transistor.

9. The single-gate field effect transistor device of claim 1 , further comprising an insulating layer provided on a surface of the active layer close to one side of the second channel, wherein the second channel is formed by the carriers generated by injected charges in the insulating layer through electrostatic induction at the channel region close to the insulating layer.

10. The single-gate field effect transistor device according to claim 9 , wherein an areal density of the carrier in the second channel is greater than the areal density of the carrier in the first channel when the turn-on voltage is applied to the transistor.

11. The single-gate field effect transistor device of claim 1 , further comprising a semiconductor material layer provided on a surface of the active layer close to one side of the second channel, wherein the active layer and the semiconductor material layer form a heterostructure,
wherein the second channel is formed by a two-dimensional electron gas channel or a two-dimensional hole gas channel distributed in the heterostructure; or, the second channel is formed by the two-dimensional electron gas channel or the two-dimensional hole gas channel formed by surface-treating of the channel region.

12. The single-gate field effect transistor device according to claim 11 , wherein an areal density of the carriers in the second channel is greater than the areal density of the carriers in the first channel when the turn-on voltage is applied to the transistor.

13. The single-gate field effect transistor device of claim 1 , wherein the source region and the drain region are a doped semiconductor or a Schottky source/drain.

14. The single-gate field effect transistor device of claim 1 , wherein a gate of the single-gate field effect transistor device is a MOS structure gate or a Schottky junction gate.

15. The single-gate field effect transistor device of claim 1 , wherein the active layer comprises at least two semiconductor materials that change along a thickness direction or a planar extension direction of the active layer.

16. A method for modulating a drive current of a single-gate field effect transistor device, comprising:
forming a depletion-mode second channel in an active layer of the field effect transistor device when the transistor is turned off, the second channel dose not electrically connect with a source region and a drain region of the field effect transistor device; and
controlling at least one of a first channel and the second channel formed in the active layer to inject carriers into the other channel when the transistor is turned on, so that current conduction occurs between the source region and the drain region and carriers of the second channel contribute to an on-state current of the transistor; wherein the first channel and the second channel are of a same polarity.

Assignees

• Univ Soochow

Inventors

• Wang Mingxiang
• Zhao Jinfeng
• Zhang Dongli
• Wang Huaisheng

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D64/647

  Schottky drain or source electrodes for IGFETs · CPC title

• H10D30/472

  having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D30/637 Primary

  Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs · CPC title