Transistor device and fabrication method

Patent metadata

Field	Value
Publication number	US-9136183-B2
Application number	US-201314143623-A
Country	US
Kind code	B2
Filing date	Dec 30, 2013
Priority date	Jan 8, 2013
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

Fabrication methods for junctionless transistor and complementary junctionless transistor. An isolation layer doped with a first-type ion is formed on a semiconductor substrate and an active layer doped with a second-type ion is formed on the isolation layer. The active layer includes a first portion between a second portion and a third portion of the active layer. Portions of the isolation layer under the second and third portions of the active layer are removed to suspend the second and third portions of the active layer. A gate structure is formed on the first portion of the active layer. A source and a drain are formed by doping the second portion and the third portion of the active layer with the second-type ion on both sides of the gate structure. The source and the drain have a same doping type as the first portion of the active layer.

First claim

What is claimed is:

1. A method for forming a complementary junctionless transistor device comprising:
providing a semiconductor substrate, wherein the semiconductor substrate includes an N-field-effect transistor (NFET) portion and a P-field-effect transistor (PFET) portion neighboring with each other;
forming an isolation layer on the semiconductor substrate and an active layer on the isolation layer, wherein the active layer and the isolation layer are made of materials havin…

Assignees

• Semiconductor Mfg Int Shanghai

Inventors

• Xiao De Yuan

Classifications

• H10D62/822

  Electricity · mapped topic

• H10D84/08

  Electricity · mapped topic

• H10D84/05

  Electricity · mapped topic

• H10D62/371

  Electricity · mapped topic

• H10D62/116

  Electricity · mapped topic